SLUUBG6 May 2017 BQ25700A , BQ25703A
The bq2570x evaluation modules are complete charger modules for evaluating an SMBUS or I2C-controlled buck boost charge using the bq2570x devices.
The bq2570x EVM does not include the EV2400 interface board. To evaluate the bq2570x EVM, order an EV2400 interface board separately.
The bq2570x is a synchronous NVDC-1 battery buck boost charge controller, offering a low component count, high efficiency solution for space-constrained, multi-chemistry battery charging applications.
The NVDC-1 configuration allows the system to be regulated at the battery voltage, but not drop below the system minimum voltage. The system keeps operating even when the battery is completely discharged or removed. When load power exceeds the input source rating, the battery supplement mode prevents the input source from being overloaded.
The bq2570x charges the battery from a wide range of input sources including a 5-V USB adapter to a high-voltage USB PD source and traditional adapters.
During power up, the charger sets the converter to buck, boost, or buck-boost configuration based on the input source and battery conditions. During the charging cycle, the charger automatically transits among buck, boost, and buck-boost configuration without host control.
The bq2570x monitors adapter current, battery current, and system power. The flexibly programmed PROCHOT output goes directly to the CPU for throttle back, when needed.
For more details on register functions, see the data sheets – bq25700A (SLUSCQ8) and bq25703A (SLUSCU1).
Table 1 lists the I/O descriptions.
Jack | Description |
---|---|
J1–VIN | Input: positive terminal |
J1–GND | Input: negative terminal (ground terminal) |
J2-ILIM_control | External converter disable; logic high to pull the ILIM pin down |
J2-CHRG_OK | CHRG_OK output |
J2-ENZ_OTG | External OTG disable pin |
J2-CELL_control | External battery removal control; logic high to pull the CELL pin down |
J3–3V3 | Onboard 3.3-V output |
J3–SDA | SMBUS or I2C SDA |
J3-SCL | SMBUS or I2C SCL |
J3-GND | Ground |
J4-CMPOUT | CMPOUT pin output |
J4-GND | Ground |
J4-CMPIN | External CMPIN pin input |
J5-BAT | Connected to battery pack output |
J5-GND | Ground |
J6-SYS | Connected to system output |
J6-GND | Ground |
Table 2 displays the controls and key parameters settings.
Jack | Description | Factory Setting |
---|---|---|
JP1
JP7 |
Inrush control setting:
spa1. Bypass inrush control circuit spa1. JP1 on: bypasses input FETs Q9 and Q10 external selector spa1. spa1. JP7 top two connection (pin 2 is connected to pin 3): VBUS pin on ACP spa2. Enable inrush control circuit spa2. JP1 off: CHRG_OK controls Q9 and Q10 external selector spa2. JP7 bottom two connection: VBUS pin on VIN |
Bypass inrush control circuit:
spaJP1 installed spaJP7 top two position installed spa(pin2 is connected pin3) |
JP2
JP3 JP4 |
CELL setting:
spa1S: JP2, JP3, JP4 all open, measure CELL pin voltage 1.2 V spa2S: JP2 closed, JP3 and JP4 open, measure CELL pin voltage 2.7 V spa3S: JP3 closed, JP2 and JP4 open, measure CELL pin voltage 3.5 V spa4S: JP2, JP3 closed, JP4 open, measure CELL pin voltage 4.2 V Bat sparemoval, short JP4 |
2S setting: JP2 installed JP3, JP4 all open |
JP5 | Jumper on: Pre-bias ILIM_HIZ
Jumper off: Ground ILIM_HIZ |
Installed |
JP6 | For input current setting:
spa Jumper on: ILIM_HIZ LOW. spa Jumper off: Allow pre-bias ILIM_HIZ |
Not installed |
JP8 | Jumper on: On-board LDO to drive the EVM 3V3
Jumper off: disconnect on-board LDO to drive the EVM 3V3 |
Installed |
Table 3 lists the recommended operating conditions.
Symbol | Description | MIN | TYP | MAX | Unit |
---|---|---|---|---|---|
Supply voltage, VIN | Input voltage from ac adapter input | 3.5 | 5/12/19 | 24 | V |
Battery voltage, VBAT | Voltage applied at VBAT terminal | 0 | 19.2 | V | |
Supply current, IAC | Maximum input current from ac adapter input | 0 | 3 | A | |
Output current, Iout | Output current | 0 | 8 | A | |
Operating junction temperature range, TJ | 0 | 125 | °C |