SLUUC27C June   2019  – July 2022 BQ25611D , BQ25619

 

  1.   BQ25611D, BQ25619 (BMS025) Evaluation Module
  2.   Trademarks
  3. 1Introduction
    1. 1.1 EVM Features
    2. 1.2 I/O Descriptions
  4. 2Test Summary
    1. 2.1 Equipment
    2. 2.2 Equipment Setup
    3. 2.3 Software Setup
    4. 2.4 Test Procedure
      1. 2.4.1 Initial Settings
      2. 2.4.2 Communication Verification
      3. 2.4.3 Charger Mode Verification
      4. 2.4.4 Boost Mode Verification
      5. 2.4.5 Evaluation Results
      6. 2.4.6 Helpful Tips
  5. 3PCB Layout Guideline
  6. 4Board Layout, Schematic, and Bill of Materials
    1. 4.1 Board Layout
    2. 4.2 Schematics
    3. 4.3 Bill of Materials
  7. 5Revision History

3 PCB Layout Guideline

Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the components minimizing high-frequency current path loop is important to prevent electrical and magnetic field radiation and high-frequency resonant problems. This PCB layout priority list must be followed in the order presented for proper layout:

  1. Place the input capacitor as close as possible to the PMID pin and GND pin connections and use the shortest copper trace connection or GND plane.
  2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a short copper trace connection or GND plane.
  4. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point or use a 0-Ω resistor to tie analog ground to power ground.
  5. Use a single ground connection to tie the charger power ground to the charger analog ground just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
  6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
  7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other layers.
  8. The via size and number should be enough for a given current path.

See the EVM design for the recommended component placement with trace and via locations. For the QFN information, refer to Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB Attachment Application Report.