SLUUC72A September 2020 – October 2021 TPS542A50
The TPS542A50EVM-059 is provided with input/output connectors and test points as shown in Table 4-2. A power supply capable of supplying at least 5 A at the desired EVM input voltage must be connected to J1_2 through a pair of 20-AWG or greater wires. The load must be connected to J2_2 through a pair of 18-AWG or greater wires. The maximum load current capability of the top ciricuit is 12 A, as limited by R7_2.
Wire lengths must be minimized to reduce losses and parasitic inductance in the wires. PVIN+_2 (TP1_2) provides a tets point to monitor the VIN input voltages with PVIN-_2 (TP2_2) providing a convenient reference to PGND. VOUT+_2 (TP6_2) is used to monitor the output voltage with VOUT-_2 (TP7_2) providing a reference to PGND.
Connection and Test Points | Description |
---|---|
J1_2 | VIN, PGND connection (see Table 1-1 for input voltage range) |
J2_2 | VOUT, PGND connection: 5.5 V at 15 A maximum (default is 1 V out at 12 A) |
J3_2 | Enable configuration |
J4_2 |
Output current sensing points when using function generator as load control signal |
PVIN+_2 (TP1_2), PVIN-_2 (TP2_2) | VIN voltage sensing test points |
VOUT+_2 (TP6_2), VOUT-_2 (TP7_2) | VOUT voltage sensing test points |
AVIN_2 (TP3_2) | AVIN voltage sensing test points |
VREG_2 (TP4_2) | VREG voltage sensing test point |
SW+_2 (TP5_2), SW-_2 (TP18_2) | SW node sensing test points |
CHA_2 (TP9_2), CHB_2 (TP8_2) |
Loop measurement test points |
SCL2 (TP10_2), SDA2 (TP11_2) | I2C connections |
EN_2 (TP14_2) |
EN pin test point |
PGD_2 (TP13_2) |
Open-drain PGD test point |
SYNC2 (TP12_2) | For connecting and measuring external clock synchronization |
AGND_2 (TP15_2, TP16_2, TP17_2) |
AGND connection - multiple provided to reduce oscilloscope ground probe loop inductance |
PGND_2 (TP18_2, TP19_2) |
PGND connection |
FGEN+_2 (TP20_2), FGEN-_2 (TP21_2) |
Function generator connection points - referenced to PGND |