SLUUC73A March   2020  – December 2023 BQ25616

 

  1.   1
  2.   BQ25616, BQ25616J BMS026 Evaluation Module
  3.   Trademarks
  4. 1Introduction
    1. 1.1 EVM Features
    2. 1.2 I/O Descriptions
  5. 2Test Summary
    1. 2.1 Equipment
    2. 2.2 Equipment Setup
    3. 2.3 Test Procedure
      1. 2.3.1 Initial Settings
      2. 2.3.2 Charge Mode Verification
      3. 2.3.3 Boost Mode Verification
      4. 2.3.4 Helpful Tips
  6. 3PCB Layout Guideline
  7. 4Board Layout
  8. 5Schematic
  9. 6Bill of Materials
  10. 7Revision History

3 PCB Layout Guideline

Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the components minimizing high-frequency current path loop is important to prevent electrical and magnetic field radiation and high-frequency resonant problems. This PCB layout priority list must be followed in the order presented for proper layout:

  1. Place the input capacitor as close as possible to the PMID pin and PGND pin connections and use the shortest copper trace connection or PGND plane.
  2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a short copper trace connection or PGND plane.
  4. Route and connect analog ground (AGND) separately from the power ground (PGND).Connect AGND and PGND together using a power pad as the single ground connection point or use a 0-Ω resistor to tie.
  5. Use a single ground connection to tie PGND to the charger ANGD just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
  6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
  7. Note the importance that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Make sure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other layers.
  8. The via size and number is enough for a given current path.

See the EVM design for the recommended component placement with trace and via locations. For the QFN information, see Quad Flatpack No-Lead Logic Packages and QFN/SON PCB Attachment.