SLUUC76B November   2019  – April 2021 TPS566231

 

  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Output Voltage Setpoint
  5. 4Test Setup and Results
    1. 4.1 Input/Output Connections
    2. 4.2 Start-Up Procedure
    3. 4.3 Start-Up
    4. 4.4 Shut-Down
    5. 4.5 Output Voltage Ripple
  6. 5Board Layout
    1. 5.1 Layout
  7. 6Board Profile, Schematic, and List of Materials
    1. 6.1 Board Profile
    2. 6.2 Schematic
    3. 6.3 List of Materials
  8. 7References
  9. 8Revision History

Layout

The board layout for the TPS566231EVM is shown in Figure 5-1 and Figure 5-2 to Figure 5-5. TPS566231EVM is with four layers, The top layer contains the main power traces for VIN, VOUT and GND. Also on the top layer are connections for the pins of the TPS566231 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C1, C2, C3 and C4 are located as close to Vin pins and PGND pins of the IC as possible. The input and output connectors, test points and all of the components are located on the top side. The bottom layer is a ground plane along with signal ground copper fill and the feed back trace from the point of regulation to the top of the resistor divider network. Two inner layers are ground plane.

GUID-BA9D7D4F-237D-4B37-B61C-9FC9D61EC285-low.gifFigure 5-1 Top Assembly
GUID-23EB18D1-2566-4FD8-8679-3767BFECB372-low.gifFigure 5-2 Top Layer
GUID-FCA2336B-410D-44D5-913B-4524E880661F-low.gifFigure 5-3 Inner1 Layer
GUID-4F2E0F1A-7B69-480A-B85B-01DD01CF4756-low.gifFigure 5-4 Inner2 Layer
GUID-848704FE-9C78-4614-A060-98DC4A433AAA-low.gifFigure 5-5 Bottom Layer