SLUUCB0 August 2021 TLIN1021A-Q1 , TLIN1039-Q1
Use the following equipment to evaluate the performance of the TLIN1039-Q1 and TLIN1021A-Q1 devices:
Designator | Description |
---|---|
TP1 | Test point to observe the INH pin |
TP2 | Test point to GND |
TP3 | Test point to GND |
TP4 | Test point to observe the VCC supply |
TP5 | Test point to observe the EN pin |
TP6 | Test point to observe the TXD pin |
TP7 | Test point to observe the RXD pin |
J1 | 6-pin (3x2) header to observe/inject various logic signals on
the U1 device
|
J2 | 2-pin (2x1) header for supplying or monitoring VSUP |
J3 | 3-pin (3x1) header to observe the LIN bus and to supply VBAT |
J4 | 2-pin (2x1) header connecting the commander mode external pull-up to the LIN bus. If shunted, U1 is in commander mode, if left open U1 is in responder mode. |
J5 | 3-pin (3x1) header that has the same function as J3 |