SLUUCB6A June   2020  – August 2022 TPS23734

 

  1.   TPS23734EVM-094 Evaluation Module
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  4. 2Electrical Specifications
  5. 3Description
  6. 4Schematic and Bill of Materials
  7. 5General Configuration and Description
    1. 5.1 Physical Access
  8. 6TPS23734EVM-094 Performance Data
    1. 6.1 Startup to PSE and DC/DC Startup
    2. 6.2 Transient Response
    3. 6.3 Efficiency
    4. 6.4 Load Regulation
    5. 6.5 Hiccup Performance During an Output Short and Recovery
    6. 6.6 Bode Plots
  9. 7EVM Assembly Drawings and Layout Guidelines
    1. 7.1 PCB Drawings
    2. 7.2 Layout Guidelines
    3. 7.3 EMI Containment
  10. 8Bill of Materials
  11. 9Revision History

EMI Containment

  • Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).
  • Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes (minimize exposed radiating surface). Hide copper associated with switching nodes under shielded magnetics, where possible.
  • Use copper ground planes (possible stitching) and top-layer copper floods (surround circuitry with ground floods).
  • Use a 4-layer PCB, if economically feasible (for better grounding).
  • Minimize the amount of copper area associated with input traces (to minimize radiated pickup).
  • Heat sink the quiet side of components instead of the switching side, where possible (like the output side of inductor).
  • Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane. Use Bob Smith plane as a ground shield on input side of PCB (creating a phantom or literal earth ground).
  • Use the LC filter at DC-to-DC input.
  • Dampen high-frequency ringing on all switching nodes, if present (allow for possible snubbers).
  • Control rise times with gate-drive resistors and possibly snubbers.
  • Switching frequency considerations.
  • Use of EMI bridge capacitor across isolation boundary (isolated topologies).
  • Observe the polarity dot on inductors (embed noisy end).
  • Use of ferrite beads on input (allow for possible use of beads or 0-Ω resistors).
  • Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as boundary line).
  • Balance efficiency versus acceptable noise margin.
  • Possible use of common-mode inductors.
  • Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations).
  • End-product enclosure considerations (shielding).