SLUUCD0A March   2024  – August 2024 BQ25758

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 General Texas Instruments High Voltage Evaluation (TI HV EMV) User Safety Guidelines
      1. 1.4.1 General Safety Information
  7. 2Hardware
    1. 2.1 Board Parameters
    2. 2.2 IO and Jumper Descriptions
    3. 2.3 Recommended Operating Conditions
    4. 2.4 Equipment
    5. 2.5 Equipment Setup
  8. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  9. 4Revision History

2.3 Recommended Operating Conditions

Table 2-5 Recommended Operating Conditions for BQ25758EVM and BQ25758AEVM
Description MIN TYP MAX UNIT
VIN (J1) Input voltage to the EVM 4.2 55(1) V
VOUT (J3) Output voltage of the EVM 3.3 55(1) V
IIN (J1) Input current of the EVM 10(3)(4) A
IOUT (J3) Output current of the EVM 10(3) A
Regulator output power Output power of the EVM 400(3) W
EXT_DRV (J6) Voltage applied to DRV_SUP pin of the regulator 4 11 V
EVM operating ambient temperature (TA) 25(2) °C
(1) Due to the high di/dt and dv/dt electrical flow associated with switch-mode power supplies, nodes on the EVM can have high spike above input voltage (in buck mode) or output voltage (in boost mode) level. Switch node voltage can swing up to "input or output + inductive spike" level. High side gate drives can swing up to "switch node voltage + 11V (DRV_SUP supply voltage dependent) + gate drive inductive spike" level. Safety precautions must be observed at all times.
(2) Connectors, bump-ons, jumpers on the EVM are not a good choice for evaluation under temperature greatly deviated from room temperature of 25°C. Please refer to BOM for temperature rating of board components.
(3) Thermal monitoring (for example, using a thermal camera) is recommended if power stage output current > 5A or total output power > 100W.
(4) Default EVM input current limit is set to 8A through the IIN pin. The current limiting feature can be disabled by setting EN_IIN_PIN bit to '0', changing IIN pin resistor, or shorting IIN pin to PGND through JP11.