SLUUCD1A April   2020  – April 2022 TPS62860

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification
    3. 1.3 Modifications
      1. 1.3.1 IC U1 Operation
  3. 2Setup
    1. 2.1 Input and Output Connector Description
      1. 2.1.1  J1, Pin 1 and 2 – VIN
      2. 2.1.2  J1, Pin 3 and 4 – S+/S-
      3. 2.1.3  J1, Pin 5 and 6 – GND
      4. 2.1.4  J2, Pin 1 and 2 – VOUT
      5. 2.1.5  J2, Pin 3 and 4 – S+/S-
      6. 2.1.6  J2, Pin 5 and 6 – GND
      7. 2.1.7  JP1 – EN
      8. 2.1.8  JP3 – VSEL1
      9. 2.1.9  JP4 - VSEL2
      10. 2.1.10 JP5 – PG
    2. 2.2 Setup
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

4.2 Bill of Materials

Table 4-1 lists the EVM bill of materials.

Table 4-1 TPS628601EVM-1 09 Bill of Materials (BOM)
Designator Quantity Value Description Package Reference PartNumber Manufacturer
C1 1 4.7 μF

CAP, CERM, 4.7 μF, 6.3

V, ± 20%, X5R, 0402

 0402 GRM155R60J475ME47D MuRata
C3 1 47 μF

CAP, CERM, 47 μF, 6.3

V, ± 20%, X5R, 0805

 0805 GRM21BR60J476ME15L MuRata
C4 1 10 μF CAP, CERM, 10 μF, 6.3V, +/- 20%, X5R, 0402 0402 GRM155R60J106ME15D MuRata
L1 1 1 μH Inductor, Shielded, MetalComposite, 1 µH, 2.7 A,0.057 Ω, SMD 1.6x2mm DFE201610E-1R0M=P2 MuRata
R3 1 100k RES, 100 k, 5%, 0.1 W,0603 0603 CRCW0603100KJNEAC Vishay-Dale
U1 1 1.8-V to 5.5-V Input,0.6A Synchronous Step- Down Converter with VSEL Interface DSBGA8 TPS628601YCH Texas Instruments