SLUUCD2A november   2020  – august 2023 TPS23731

 

  1.   1
  2.   TPS23731EVM-095 Evaluation Module
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  5. 2Electrical Specifications
  6. 3Description
  7. 4General Configuration and Description
    1. 4.1 Physical Access
  8. 5TPS23731EVM-095 Performance Data
    1. 5.1 Startup Response
    2. 5.2 Transient Response
    3. 5.3 Efficiency
    4. 5.4 Load Regulation
    5. 5.5 Hiccup Performance During an Output Short and Recovery
    6. 5.6 Bode Plots
  9. 6EVM Assembly Drawings and Layout Guidelines
    1. 6.1 PCB Drawings
    2. 6.2 Layout Guidelines
    3. 6.3 EMI Containment
  10. 7Schematic
  11. 8Bill of Materials
  12. 9Revision History

6.2 Layout Guidelines

The layout of the PoE front end should follow power and EMI or ESD best-practice guidelines. A basic set of recommendations includes:

  • It is recommended having at least 8 vias (PAD G) and 5 vias on (PAD S) connecting the exposed thermal pad through a top layer plane (2 oz copper recommended) to a bottom VSS plane (2 oz. copper recommended) to help with thermal dissipation.
  • Place the primary MOSFET near the power transformer and keep the current sense resistor close to source of the MOSFET to minimize the primary loop. The same is true for the secondary MOSFETs. Keep the MOSFETs close to the transformer, and associated components as close together as possible to minimize the loop.
  • Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode bridges, TVS and 0.1-μF capacitor, and TPS23731 converter input bulk capacitor.
  • Make all leads as short as possible with wide power traces and paired signal and return.
  • No crossovers of signals from one part of the flow to another are allowed.
  • Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage rails and between the input and an isolated converter output.
  • Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay copper fills in the power path.
  • Place the Schotty diode between VSS and RTN as close to the IC as possible, preferably on directly on the opposite side of the board (ex. The TPS23731EVM-095 places the IC on the top side, so the diode is on the bottom side directly underneath it).

The DC-to-DC converter layout benefits from basic rules such as:

  • Having at least 4 vias (VDD) near the power transformer pin connected to VDD through multiple layer planes to help with thermal dissipation of the power transformer.
  • Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses, which include the power semiconductors and magnetics
  • Minimize the trace length of high current power semiconductors and magnetic components
  • Use the ground plane for the switching currents carefully
  • Keep the high-current and high-voltage switching away from low-level sensing circuits including those outside the power supply
  • Proper spacing around the high-voltage sections of the converter