SLUUCE9A December   2020  – April 2021 TPS543820 , TPS543820E

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  3. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Switching Frequency (FSEL Pin)
    3. 2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
    4. 2.4 Adjustable UVLO
  4. 3Test Setup and Results
    1. 3.1  Input/Output Connections
    2. 3.2  Efficiency
    3. 3.3  Output Voltage Regulation
    4. 3.4  Load Transient and Loop Response
    5. 3.5  Output Voltage Ripple
    6. 3.6  Input Voltage Ripple
    7. 3.7  Synchronizing to a Clock
    8. 3.8  Start-up and Shutdown with EN
    9. 3.9  Start-up and Shutdown with VIN
    10. 3.10 Start-up Into Pre-Bias
    11. 3.11 Hiccup Current Limit
    12. 3.12 Overvoltage Protection
    13. 3.13 Thermal Performance
  5. 4Board Layout
    1. 4.1 Layout
  6. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  7. 6Revision History

3.3 Output Voltage Regulation

Figure 3-6 and Figure 3-7 show the load and line regulation for U1. Figure 3-8 and Figure 3-9 show the load and line regulation for U2.

GUID-20201209-CA0I-H9NZ-8P7L-KM5HQL4PLDBG-low.svgFigure 3-6 U1 Load Regulation
GUID-20201209-CA0I-ZDZV-4VQR-JNNWFS9LKCTQ-low.svgFigure 3-8 U2 Load Regulation
GUID-20201216-CA0I-GDQN-ZRXK-5VGBSFZRTJS2-low.svgFigure 3-7 U1 Line Regulation
GUID-20201209-CA0I-WX1W-CNWG-XX1NZJQM1PVJ-low.svgFigure 3-9 U2 Line Regulation