SLUUCF2C January 2021 – May 2022 BQ769142
Class | Subclass | Name | Type | Min | Max | Default | Unit |
---|---|---|---|---|---|---|---|
Settings | Protection | DSG FET Protections C | U1 | 0x00 | 0xFF | 0xE2 | Hex |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCD3 | SCDL | OCDL | RSVD_0 | RSVD_0 | RSVD_0 | HWDF | RSVD_0 |
Description: This bitfield configures which protections will disable the DSG FET. DSG FET action for any non-reserved bits may be individually selected.
Bit | Field | Default | Description |
---|---|---|---|
7 | OCD3 | 1 | Overcurrent in Discharge 3rd Tier Protection 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |
6 | SCDL | 1 | Short Circuit in Discharge Latch 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |
5 | OCDL | 1 | Overcurrent in Discharge Latch 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |
1 | HWDF | 1 | Host Watchdog Fault 0 = DSG FET is not disabled when protection is triggered. 1 = DSG FET is disabled when protection is triggered. |