SLUUCF2C January 2021 – May 2022 BQ769142
The 0x0075 DASTATUS5() subcommand provides voltage measurements of the REG18 LDO voltage, the VSS pin, as well as calculated values for the minimum, maximum, and sum of cell voltage measurements. It also provides the readings used for cell and FET temperature, minimum, maximum, and average cell temperature, and both CC1 and CC3 current values.
Since the VREF2 measurement is measured by the voltage ADC using VREF1, the REG18 voltage measurement provides information on the ratio of one reference versus the other and should stay approximately constant. This measurement can be used as a diagnostic check to determine if one reference changes value versus the other.
The VSS measurement is included as an additional diagnostic measurement to ensure that the ADC input mux is working properly. This measurement should normally result in a value near 0. If an internal fault were to occur that caused the ADC input mux to be stuck at a particular setting, such as a cell input, then the VSS measurement would be significantly higher. If the mux were stuck at a setting such as an interconnect measurement or VSS, the cell voltage measurements would be reported as very low voltage.
The Battery Voltage Sum is the sum of all enabled cell voltage measurements, reported in units of cV (10 mV). This value can be compared with the 0x34 Stack Voltage() and used as a diagnostic check.
The 32-bit raw CC2 counts and raw CC3 counts data have an LSB value of approximately VREF2 / (5 × 223) ≅ 1.24 V / (5 × 223) ≅ 29.56 nV.
Table 5-5 provides further details.
Subcommand Address | Bytes Within Block | Name | Unit |
---|---|---|---|
0x0075 | 0–1 | VREG18 | 16-bit ADC counts |
2–3 | VSS | 16-bit ADC counts | |
4–5 | Max Cell Voltage | mV | |
6–7 | Min Cell Voltage | mV | |
8–9 | Battery Voltage Sum | cV | |
10–11 | Avg Cell Temperature | 0.1 K | |
12–13 | FET Temperature | 0.1 K | |
14–15 | Max Cell Temperature | 0.1 K | |
16–17 | Min Cell Temperature | 0.1 K | |
18–19 | Avg Cell Temperature | 0.1 K | |
20–21 | CC3 Current | userA | |
22–23 | CC1 Current | userA | |
24–27 | CC2 Counts | 32-bit ADC counts | |
28–31 | CC3 Counts | 32-bit ADC counts |
The 0x0076 DASTATUS6() subcommand provides the accumulated charge value and associated timer. It also includes the 32-bit raw ADC count for the CFETOFF, DFETOFF, ALERT, TS1, and TS2 pin measurements, which can be used for customer calibration of the general-purpose ADC input measurement capability of the device.
The 32-bit raw ADC counts data for the CFETOFF, DFETOFF, ALERT, TS1, TS2, TS3, HDQ, DCHG, and DDSG pins has a different LSB value, depending on whether the pin is configured for thermistor measurement mode or general purpose ADC (ADCIN) input mode. When configured for thermistor measurement, the raw ADC counts have an LSB of approximately 5 / 3 × 1.8 V / 223 ≅ 0.358 μV. When configured for ADCIN measurement, the raw ADC counts have an LSB of approximately 5 / 3 × VREF1 / 223 ≅ 5 / 3 × 1.212 V / 223 ≅ 0.241 μV.
The details of this subcommand are shown below.
Subcommand Address | Bytes Within Block | Name | Unit |
---|---|---|---|
0x0076 | 0–3 | Accumulated charge (integer portion) | 32-bit signed integer portion in userAh |
4–7 | Accumulated charge (fractional portion), initialized to 0.5 userAh when reset | 32-bit fractional portion in userAh | |
8–11 | Accumulated Time | 32-bit unsigned integer in seconds | |
12–15 | CFETOFF Counts | 32-bit ADC counts | |
16–19 | DFETOFF Counts | 32-bit ADC counts | |
20–23 | ALERT Counts | 32-bit ADC counts | |
24–27 | TS1 Counts | 32-bit ADC counts | |
28–31 | TS2 Counts | 32-bit ADC counts |
The 0x0077 DASTATUS7() subcommand provides the 32-bit raw ADC count for the TS3, HDQ, DCHG, and DDSG pin measurement, which can be used for customer calibration of the general-purpose ADC input measurement capability of the device. The details of this subcommand are shown below.
Subcommand Address | Bytes within Block | Name | Unit |
---|---|---|---|
0x0077 | 0–3 | TS3 Counts | 32-bit ADC counts |
4–7 | HDQ Counts | 32-bit ADC counts | |
8–11 | DCHG Counts | 32-bit ADC counts | |
12–15 | DDSG Counts | 32-bit ADC counts | |
16–31 | Reserved | - |