SLUUCF2C January 2021 – May 2022 BQ769142
The BQ769142 device includes an integrated charge pump and high-side NFET drivers for driving CHG and DSG protection FETs. The charge pump uses an external capacitor connected between the BAT and CP1 pins that is charged to an overdrive voltage when the charge pump is enabled (controlled using the Settings:FET:Chg Pump Control[CPEN] configuration bit). Due to the time required for the charge pump to bring the overdrive voltage on the external CP1 pin to full voltage, it is recommended to leave the charge pump powered whenever it may be needed quickly to drive the CHG or DSG FETs.
The DSG FET driver includes a special option (denoted source follower mode) to drive the DSG FET with the BAT pin voltage during SLEEP mode. This capability is included to provide low power in SLEEP mode, when there is no significant charge or discharge current flowing. It is recommended to keep the charge pump enabled even when the source follower mode is enabled, so whenever a discharge current is detected, the device can quickly transition to driving the DSG FET using the charge pump voltage. The source follower mode is enabled by setting the Settings:FET:Chg Pump Control[SFMODE_SLEEP] configuration bit. The source follower mode is not intended to be used when significant charging or discharging current is flowing, since the FET will exhibit a large drain-source voltage and may undergo excessive heating.
The overdrive level of the charge pump voltage can be set to 5.5 V or 11 V, using the Settings:FET:Chg Pump Control[LVEN] configuration bit. In general, the 5.5 V setting results in lower power dissipation when a FET is being driven, while the higher 11 V overdrive reduces the on-resistance of the FET. If a FET exhibits significant gate leakage current when driven at the higher overdrive level, this can result in a higher device current for the charge pump to support this. In this case, using the lower overdrive level can reduce the leakage current and thus the device current.
The BQ769142 device supports a system with FETs in a series or parallel configuration, where the parallel configuration includes a separate path for the charger connection versus the discharge (load) connection. The control logic for the device operates slightly differently in these two cases, which is set based on the Settings:FET:FET Options[SFET] configuration bit. See Section 6.2.3.1 for more information on this operation.
The FET drivers in the BQ769142 device can be controlled in several different manner, depending on customer requirements:
| Fully autonomous | |
| The BQ769142 device can detect protection faults and autonomously disable the FETs, monitor for a recovery condition, and autonomously reenable the FETs, without requiring any host processor involvement. | |
| This mode is enabled by setting the Settings:Manufacturing:Mfg Status Init[FET_EN] configuration bit. The FETs may be disabled when a fault occurs based on settings in Settings:Protection:CHG FET Protections A/B/C and Settings:Protection:DSG FET Protections A/B/C. | |
| Partially autonomous | |
| The BQ769142 device can detect protection faults and autonomously disable the FETs. When the host receives an interrupt and recognizes the fault, the host can write the 0x0093 DSG_PDSG_OFF() or 0x0094 CHG_PCHG_OFF() or 0x0095 ALL_FETS_OFF() commands to keep the FETs off until the host decides to release them. The 0x0097 FET_CONTROL() subcommand can also be used to enable or disable each FET individually. | |
| Alternatively, the host can assert the CFETOFF or DFETOFF pins to keep the FETs off. When the host decides to allow the FETs to turn on again, it writes the 0x0096 ALL_FETS_ON() command, and the BQ769142 device will reenable the FETs if nothing is blocking them being reenabled (such as fault conditions still present, or the CFETOFF or DFETOFF pins are asserted). | |
| Manual control | |
| The BQ769142 device can detect protection faults and provide an interrupt to a host processor over the ALERT pin. The host processor can read the status information of the fault over the communication bus (if desired) and can quickly force the CHG or DSG FETs off by driving the CFETOFF or DFETOFF pins from the host processor, or using the 0x0093 DSG_PDSG_OFF() or 0x0094 CHG_PCHG_OFF(), 0x0095 ALL_FETS_OFF(), or 0x0097 FET_CONTROL() subcommands. | |
| When the host decides to allow the FETs to turn on again, it writes the 0x0096 ALL_FETS_ON() command or deasserts the CFETOFF and DFETOFF pins, and the BQ769142 device will reenable the FETs if nothing is blocking them being reenabled. |
The status of the FET drivers is provided by the [DSG_FET] and [CHG_FET] bits in the 0x7F FET Status() command. Depending on the device mode and fault status, there may be cases when only one FET is enabled, and the other FET is disabled. For example:
During SLEEP mode, the CHG FET may be disabled (if Settings:FET:FET Options[SLEEPCHG] is cleared), while the DSG FET is enabled.
If a COV fault has occurred, the CHG FET may be disabled, while the DSG FET may still be enabled, to allow discharge.
If a CUV fault has occurred, the DSG FET may be disabled, while the CHG FET may still be enabled, to allow charging.
If the device is in series FET configuration and a single FET is on, it is possible for current to flow through the off-FET body diode. This current can damage the FET if high enough for a long enough time. In this case, when the BQ769142 device is autonomously controlling the FETs, if a current is detected above a level given by Settings:Protection:Body Diode Threshold, the device will automatically turn on the off-FET, to prevent further damage. This configuration register should be a positive value, it is used as a charging current level when deciding to turn on the DSG FET, and it is used as a discharging current level when deciding to turn on the CHG FET.
If the high-side NFET drivers will not be used in the application, the charge pump and FET drivers can be disabled by clearing the Settings:FET:Chg Pump Control[CPEN] and Settings:FET:FET Options[FET_CTRL_EN] configuration bits.