SLUUCF2C January 2021 – May 2022 BQ769142
The BQ769142 device provides flexibility regarding the multifunction pins on the device, which includes the TS1, TS2, TS3, CFETOFF, DFETOFF, ALERT, HDQ, DCHG, and DDSG pins. Several of the pins can be used as active-high outputs with configurable output level. The digital output driver for these pins can be configured to drive an output powered from the REG1 LDO or from the internal REG18 LDO, and thus when asserted active-high will drive out the voltage of the selected LDO.
Note: the REG18 LDO is not capable of driving high current levels, so it is recommended to only use this LDO to provide a digital output if it will be driving a very high resistance (such as > 1 MΩ) or light capacitive load. Otherwise the REG1 should be powered and used to drive the output signal.
The options supported on each pin include:
| ALERT | |||
| Alarm interrupt output. It can be configured as follows: | |||
| Hi-Z when no alarm is triggered, versus driven low when triggered. | |||
| Driven high when no alarm is triggered, versus driven low when triggered. | |||
| Driven low when no alarm is triggered, versus driven high when triggered. | |||
| HDQ communications | |||
| Can be used for HDQ communications with a host processor. | |||
| CFETOFF | |||
| Input to control the CHG FET (that is, CFETOFF functionality). It can be configured as follows: | |||
| A high input forces the CHG FET off, a low input allows the CHG FET to be turned on (by host or device itself). | |||
| A low input forces the CHG FET off, a high input allows the CHG FET to be turned on (by host or device itself). | |||
| DFETOFF | |||
| Input to control the DSG FET (that is, DFETOFF functionality). It can be configured as follows: | |||
| A high input forces the DSG FET off, a low input allows the DSG FET to be turned on (by host or device itself). | |||
| A low input forces the DSG FET off, a high input allows the DSG FET to be turned on (by host or device itself). | |||
| Input to control both the DSG and CHG FETs (that is, BOTHOFF functionality). It can be configured as follows: | |||
| A high input forces both FETs off, a low input allows the FETs to be turned on (by host or device itself). | |||
| A low input forces both FETs off, a high input allows the FETs to be turned on (by host or device itself). | |||
| HDQ | |||
| HDQ communications | |||
| Can be used for HDQ communications with a host processor | |||
| SPI MOSI pin | |||
| MOSI pin for SPI communications | |||
| DCHG | |||
| DCHG functionality | |||
| A logic-level output corresponding to a fault, which would normally cause the CHG driver to be disabled. | |||
| DDSG | |||
| DDSG functionality | |||
| A logic-level output corresponding to a fault, which would normally cause the DSG driver to be disabled. | |||
| ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG | |||
| General purpose digital output | |||
| Can be driven high or low by command | |||
| Can be configured for an active-high output to be driven from the REG1 LDO or the REG18 LDO | |||
| Can be configured to have a weak pull-down to VSS or weak pull-up to REG1 enabled continuously | |||
| ALERT, CFETOFF, DFETOFF, TS1, TS2, TS3, HDQ, DCHG, and DDSG | |||
| Thermistor temperature measurement | |||
| A thermistor can be attached between the pin and VSS. | |||
| ADCIN | |||
| Pin can be used for general purpose ADC measurement. | |||
These pin configurations are controlled by the Settings:Configuration:ALERT Pin Config, CFETOFF Pin Config, DFETOFF Pin Config, TS1 Config, TS2 Config, TS3 Config, HDQ Pin Config, DCHG Pin Config, and DDSG Pin Config configuration registers. The [PIN_FXN1:0] bits in each configuration register determine how the pin will be used:
| PIN_FXN1 | PIN_FXN0 | Pin Function |
|---|---|---|
| 0 | 0 | Pin is used for communications, or not used at all. |
| 0 | 1 | General purpose digital output (GPO) |
| 1 | 0 | Alternate function (ALT) |
| 1 | 1 | Thermistor measurement or general purpose ADC input (AD) |
The ALT (Alternate function) setting refers to special functions that are only available on particular pins. The alternate functions available for pins are:
| Pin | ALT (Alternate Function) |
|---|---|
| ALERT | Alarm interrupt output |
| CFETOFF | CFETOFF functionality (CHG and PCHG FET control) |
| DFETOFF | DFETOFF functionality (DSG and PDSG FET control) |
| BOTHOFF functionality (combined CHG and PCHG, and DSG and PDSG FET control) | |
| DCHG | DCHG functionality (logic-level protection signal) |
| DDSG | DDSG functionality (logic-level protection signal) |
Each pin configuration register includes [OPT5:0] bits which set the operation of the pin. When a pin is configured for ALT or GPO, these bits are used as shown below.
| Bit | Function |
|---|---|
| OPT[5] | Polarity for ALERT, CFETOFF,
DFETOFF. HDQ, DCHG, and DDSG pins only. 0: selects active-high. 1: selects active-low. |
| OPT[4] | Only used for DFETOFF pin. 0: selects ALT = DFETOFF. 1: selects ALT = BOTHOFF. |
| OPT[3] | GPO drive level for ALERT, CFETOFF,
DFETOFF, HDQ, DCHG, and DDSG pins only. 0: output high drive uses REG18. 1: output high drive uses REG1. |
| OPT[2] | GPO weak pull-up control for ALERT,
CFETOFF, DFETOFF, HDQ, DCHG, and DDSG pins only. 0: weak pull-up to REG1 is disabled. 1: weak pull-up to REG1 is enabled. NOTE–this should only be selected if OPT[3] = 0 and OPT[1] = 0: |
| OPT[1] | GPO drive mode for ALERT, CFETOFF,
DFETOFF, HDQ, DCHG, and DDSG pins only. 0: pin drives tri-state when controlled to be driven "high." 1: pin drives active-high when controlled to be driven "high." |
| OPT[0] | GPO weak pulldown control for ALERT,
CFETOFF, DFETOFF, HDQ, DCHG, DDSG pins only. 0: weak pulldown to VSS is disabled. 1: weak pulldown to VSS is enabled. |
When a pin is selected for thermistor or ADCIN functionality, the OPT[5:0] bits are used as shown below.
| Bit | Function |
|---|---|
| OPT[5:4] | Pull-up control 00: selects 18 kΩ pull-up for thermistor measurement 01: selects 180 kΩ pull-up for thermistor measurement 10: selects no pull-up (used for ADCIN) |
| OPT[3:2] | Polynomial selection
for thermistor temperature measurement 00: selects Calibration:18K Temperature Model 01: selects Calibration:180K Temperature Model 10: selects Calibration:Custom Temperature Model 11: no polynomial is used, raw ADC counts are reported. |
| OPT[1:0] | Measurement type 00: general purpose ADC input 01: thermistor temperature measurement, used for cell temperature protections 10: thermistor temperature measurement, reported but not used for protections 11: thermistor temperature measurement, used for FET temperature protection |
When a pin is configured for use as a general purpose digital output, its output state can be controlled by the subcommands shown below.
| Subcommand | Description |
|---|---|
| 0x2800 CFETOFF_LO() | If the CFETOFF pin is configured as a GPO, this subcommand sets it to drive a low output. |
| 0x2801 DFETOFF_LO() | If the DFETOFF pin is configured as a GPO, this subcommand sets it to drive a low output. |
| 0x2802 ALERT_LO() | If the ALERT pin is configured as a GPO, this subcommand sets it to drive a low output. |
| 0x2806 HDQ_LO() | If the HDQ pin is configured as a GPO, this subcommand sets it to drive a low output. |
| 0x2807 DCHG_LO() | If the DCHG pin is configured as a GPO, this subcommand sets it to drive a low output. |
| 0x2808 DDSG_LO() | If the DDSG pin is configured as a GPO, this subcommand sets it to drive a low output. |
| 0x2810 CFETOFF_HI() | If the CFETOFF pin is configured as a GPO, this subcommand sets it to drive a high output. |
| 0x2811 DFETOFF_HI() | If the DFETOFF pin is configured as a GPO, this subcommand sets it to drive a high output. |
| 0x2812 ALERT_HI() | If the ALERT pin is configured as a GPO, this subcommand sets it to drive a high output. |
| 0x2816 HDQ_HI() | If the HDQ pin is configured as a GPO, this subcommand sets it to drive a high output. |
| 0x2817 DCHG_HI() | If the DCHG pin is configured as a GPO, this subcommand sets it to drive a high output. |
| 0x2818 DDSG_HI() | If the DDSG pin is configured as a GPO, this subcommand sets it to drive a high output. |