SLUUCF2C January 2021 – May 2022 BQ769142
The ALERT pin is a multifunction pin that can be configured either as ALERT (to provide an interrupt to a host processor), a thermistor input, a general purpose ADC input, a general purpose digital output, or an HDQ serial communication interface. The pin can be configured as active-high, active-low, or open-drain, to accommodate different system design preferences. When configured as the HDQ interface pin, the pin will operate in open-drain mode.
When the pin is configured to drive an active high output, the output voltage is driven from either the REG18 1.8 V LDO or the REG1 LDO (which can be programmed from 1.8 V to 5.0 V). Note: if a DC or significant transient current may be driven by this pin, then the output should be configured to drive using the REG1 LDO, not the REG18 LDO.
The BQ769142 device includes functionality to generate an alarm signal at the ALERT pin, which can be used as an interrupt to a host processor. This functionality is optional, it can be enabled by setting the Settings:Configuration:ALERT Pin Config[PIN_FXN1:0] = 0b10. When used for the alarm function, the pin can be programmed to drive the signal as an active-low or hi-Z signal, an active-high or low signal, or an active-low or high signal (that is, inverted polarity). The alarm function within the BQ769142 device includes a programmable mask, to allow the customer to decide which of many flags or events can trigger an alarm. The 0x64 Alarm Raw Status() command provides the present (unlatched) value of the bits described below:
| Bit | Name | Description |
|---|---|---|
| 15 | SSBC | Safety Status—Set if a bit in Safety Status B–C() is set. |
| 14 | SSA | Hardware Safety Status—Set if a bit in Safety Status A() is set. |
| 13 | PF | Permanent Fail Status—Set if a bit in PF Status A–D() is set. |
| 12 | MSK_SFALERT | Masked Safety Alerts—Set if a bit in Safety Alert A–C() is set and the corresponding bit in Settings:Alarm:SF Alert Mask A–C is set. |
| 11 | MSK_PFALERT | Masked Permanent Fail Alerts—Set if a bit in PF Alert A–D() is set and the corresponding bit in Settings:Alarm:PF Alert Mask A–D is set. |
| 10 | INITSTART | Initialization started (sets quickly after device powers up) |
| 9 | INITCOMP | Initialization completed (sets after device has powered and completed one measurement scan) |
| 8 | RSVD | Reserved |
| 7 | FULLSCAN | Full Voltage Scan Complete. The necessary multiple ADC scans have been completed to collect the full voltage measurement loop data (including cell voltages, pin or thermistor voltages, and so forth). This bit sets after the first full scan completes, then remains set. |
| 6 | XCHG | CHG FET is off. |
| 5 | XDSG | DSG FET is off. |
| 4 | SHUTV | Stack voltage is below Power:Shutdown:Shutdown Stack Voltage. |
| 3 | FUSE | FUSE Pin Driven. The FUSE pin is being driven by either the BQ769142 device or the secondary protector. |
| 2 | CB | Cell balancing is active |
| 1 | ADSCAN | Voltage ADC Scan Complete. A single ADC scan is complete (cell voltages are measured on each scan). This bit sets after the first ADC scan completes, then remains set. |
| 0 | WAKE | Wake. Device is wakened from SLEEP mode. |
The bits in 0x64 Alarm Raw Status() can be selected to be latched and included in the alarm interrupt output based on mask registers.
When a masked flag transitions from low to high, it latches a corresponding bit in 0x62 Alarm Status(). The [ADSCAN] and [FULLSCAN] bits are exceptions. They will be latched in 0x62 Alarm Status() when scans complete if masked, even though the corresponding bits in 0x64 Alarm Raw Status() do not toggle.
The masking is determined if the corresponding mask bit is set in the Settings:Alarm:Default Alarm Mask, Settings:Alarm:SF Alert Mask A–C, and Settings:Alarm:PF Alert Mask A–D configuration registers. The host can poll 0x62 Alarm Status(), or use the alarm interrupt signal (the OR of all bits in 0x62 Alarm Status()) mapped to the ALERT pin.
When bits are latched into 0x62 Alarm Status(), the host can read the status and clear those latched bits by writing the 0x62 Alarm Status() command with a '1' in one or more of the bits to be cleared, and '0s' in all other bits (which leaves the other bits unchanged). This prevents unintentional clearing of any additional 0x62 Alarm Status() bits that may have been set just before the clearing signal was sent from the host processor.
The 0x66 Alarm Enable() command can be read to see the present mask applied to the 0x64 Alarm Raw Status() bits. The 0x66 Alarm Enable() command can also be written by the host to change the masking during operation.
The status of the ALERT pin is provided in the 0x7F FET Status()[ALRT_PIN] register bit.