SLUUCH2 March 2021 BQ40Z50-R2
This command returns the SafetyStatus() flags on ManufacturerBlockAccess() or ManufacturerData().
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RSVD | RSVD | OCDL | COVL | UTD | UTC | PCHGC | CHGV | CHGC | OC | RSVD | CTO | RSVD | PTO | RSVD | OTF |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | CUVC | OTD | OTC | ASC DL | ASCD | ASC CL | ASCC | AOLDL | AOLD | OCD2 | OCD1 | OCC2 | OCC1 | COV | CUV |
RSVD (Bits 31–30): Reserved. Do not use. | ||
OCDL (Bit 29): Overcurrent in discharge | ||
1 = | Detected | |
0 = | Not Detected | |
COVL (Bit 28): Cell overvoltage latch | ||
1 = | Detected | |
0 = | Not Detected | |
UTD (Bit 27): Undertemperature during discharge | ||
1 = | Detected | |
0 = | Not Detected | |
UTC (Bit 26): Undertemperature during charge | ||
1 = | Detected | |
0 = | Not Detected | |
PCHGC (Bit 25): Over-precharge current | ||
1 = | Detected | |
0 = | Not Detected | |
CHGV (Bit 24): Overcharging voltage | ||
1 = | Detected | |
0 = | Not Detected | |
CHGC (Bit 23): Overcharging current | ||
1 = | Detected | |
0 = | Not Detected | |
OC (Bit 22): Overcharge | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bit 21): Reserved. Do not use. | ||
CTO (Bit 20): Charge timeout | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bit 19): Reserved. Do not use. | ||
PTO (Bit 18): Precharge timeout | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bit 17): Reserved. Do not use. | ||
OTF (Bit 16): Overtemperature FET | ||
1 = | Detected | |
0 = | Not Detected | |
RSVD (Bit 15): Reserved. Do not use. | ||
CUVC (Bit 14): Cell undervoltage compensated | ||
1 = | Detected | |
0 = | Not Detected | |
OTD (Bit 13): Overtemperature during discharge | ||
1 = | Detected | |
0 = | Not Detected | |
OTC (Bit 12): Overtemperature during charge | ||
1 = | Detected | |
0 = | Not Detected | |
ASCDL (Bit 11): Short-circuit during discharge latch | ||
1 = | Detected | |
0 = | Not Detected | |
ASCD (Bit 10): Short-circuit during discharge | ||
1 = | Detected | |
0 = | Not Detected | |
ASCCL (Bit 9): Short-circuit during charge latch | ||
1 = | Detected | |
0 = | Not Detected | |
ASCC (Bit 8): Short-circuit during charge | ||
1 = | Detected | |
0 = | Not Detected | |
AOLDL (Bit 7): Overload during discharge latch | ||
1 = | Detected | |
0 = | Not Detected | |
AOLD (Bit 6): Overload during discharge | ||
1 = | Detected | |
0 = | Not Detected | |
OCD2 (Bit 5): Overcurrent during discharge 2 | ||
1 = | Detected | |
0 = | Not Detected | |
OCD1 (Bit 4): Overcurrent during discharge 1 | ||
1 = | Detected | |
0 = | Not Detected | |
OCC2 (Bit 3): Overcurrent during charge 2 | ||
1 = | Detected | |
0 = | Not Detected | |
OCC1 (Bit 2): Overcurrent during charge 1 | ||
1 = | Detected | |
0 = | Not Detected | |
COV (Bit 1): Cell overvoltage | ||
1 = | Detected | |
0 = | Not Detected | |
CUV (Bit 0): Cell undervoltage | ||
1 = | Detected | |
0 = | Not Detected |