SLUUCH6B september   2022  – september 2023 TPS543B22

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  5. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Switching Frequency (FSEL Pin)
    3. 2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
    4. 2.4 Adjustable UVLO
  6. 3Test Setup and Results
    1. 3.1  Input/Output Connections
    2. 3.2  Efficiency
    3. 3.3  Output Voltage Regulation
    4. 3.4  Load Transient and Loop Response
    5. 3.5  Output Voltage Ripple
    6. 3.6  Input Voltage Ripple
    7. 3.7  Synchronizing to a Clock
    8. 3.8  Start-up and Shutdown with EN
    9. 3.9  Start-up and Shutdown with VIN
    10. 3.10 Start-up Into Pre-Bias
    11. 3.11 Hiccup Current Limit
    12. 3.12 Thermal Performance
  7. 4Board Layout
    1. 4.1 Layout
  8. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  9. 6Revision History

3.1 Input/Output Connections

The TPS543B22EVM is provided with input connectors, output connectors, and test points as shown in Table 3-1 and Table 3-2.

To support the minimum input voltage with the full rated load on both outputs with the default EVM, a power supply capable of supplying greater than 20 A must be connected to J1 through a pair of 18-AWG wires or better.

For U2, the load must be connected to J2 and for U1, the load must be connected to J14. Two pair of 18-AWG wires or better must be used for each connection. With the maximum current limit setting, the maximum load current capability is near 20 A before the TPS543B22 goes into current limit. Wire lengths must be minimized to reduce losses in the wires.

Test point TP30 provides a place to monitor the VIN input voltage with TP33 providing a convenient ground reference for U1. Test point TP2 provides a place to monitor the VIN input voltage with TP9 providing a convenient ground reference for U2. TP31 is used to monitor the output voltage of U1 with TP36 as the ground reference. TP1 is used to monitor the output voltage of U2 with TP16 as the ground reference.

If modifications are made to the TPS543B22EVM, then the input current can change. The input power supply and wires connecting the EVM to the power supply must be rated for the input current.

Note: For the FSEL pin of the TPS543B22 to correctly detect the resistor value connected to ground, the buffers on the EVM need to be provided a VCC voltage of 2 V to 5.5 V to go high impedance.
Table 3-1 Connectors and Jumpers
REFERENCE DESIGNATORNAMERELATED ICFUNCTION
J1 VIN Both VIN screw terminal to connect input voltage (see Table 1-1 for VIN range).
J2 VOUT_P2 U2 VOUT screw terminal to connect load to output.
J3 VOUT Select U2 VOUT selection header. Use shunt to set output voltage. See Table 2-1.
J4 ENSYNC_P2 U2 2-pin header to connect U2 buffer output enable to ground. Populate shunt to enable output of buffer. Remove shunt to make buffer output high impedance.
J6 VO_2NDSTG U2 Output Second Filter.
J7 FSEL Select U2 FSEL selection header. Use shunt to select FSEL resistor. See Table 2-2.
J8 FSEL Test U2 Test mode 1-2 use pin strap resistors. 2-3 I2C test mode.
J9 MODE Select U2 MODE selection header. Use shunt to select MODE resistor. See Table 2-3.
J10 MODE Test U2 Test mode 1-2 use pin strap resistors. 2-3 I2C test mode.
J14 VOUT_P1 U1 VOUT screw terminal to connect load to output.
J15 EN_OFF_P1 U1 2-pin header for enable. Add shunt to connect EN to ground and disable device.
J16 ENSYNC_P1 U1 2-pin header to connect U4 buffer output enable to ground. Populate shunt to enable output of buffer. Remove shunt to make buffer output high impedance.
Table 3-2 Test Points
REFERENCE DESIGNATORNAMERELATED ICFUNCTION
TP1 VOUT_P2 U2 VOUT test point. Use this for efficiency, output regulation, and bode plot measurements.
TP2 VIN_P2 U2 VIN test point. Use this for efficiency measurements.
TP3 SW_P2 U2 SW node solder mask opening.
TP4 VDRV_P2 U2 VDRV node test point.
TP5 SW_P2 U2 SW node test point.
TP6 PGOOD_P2 U2 PGOOD test point.
TP7 MSEL_P2 U2 MODE test point.
TP8 AGND_P2 U2 AGND test point.
TP9 PGND_P2 U2 PGND test point.
TP10 VCC_BUF_P2 U2 VDRV Voltage Supply to Buffer.
TP11 GOSNS U2 Remote Sense for U2.
TP12 FSEL_P2 U2 FSEL test point.
TP13 PGND U2 Ground near P2 SYNC input.
TP14 BODE-_P2 U2 Test point between voltage divider network and output voltage. Used for Bode plot measurements.
TP15 BODE+__P2 U2 Used for Bode plot measurements.
TP16 PGND_VO2_P2 U2 PGND test point. Use this for efficiency measurements.
TP17 EN__P2 U2 EN test point. If user is applying an external voltage, then the external voltage must be kept below the absolute maximum voltage of the EN pin of 6 V.
TP18 SYNC_P2 U2 SYNC test point. Supply an external clock to this test point to synchronize U1 regulators.
TP19 VO_2NDSTG U2 SMB connector to measure output voltage after second stage filter if added to EVM. When using this test point, the scope must be set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP20 VO2_PGND U2 Ground for second stage filter output.
TP21 ISNS Both Test point to measure current in load transient circuit. Gain is 20 A/V.
TP22 FGEN Both Test point to connect function generator to load transient circuit. Slowly increase amplitude and vary slew rate of function generator for desired load step.
TP23 ISNS Both Test point to measure current in load transient circuit. Gain is 20 A/V.
TP24 SW_P2 U2 SMB connector to measure SW node. When using this test point, the scope must be set for 50-Ω termination. The combination of 50-Ω termination and 450-Ω series resistance creates a 10:1 attenuation.
TP25 VOUT_P2 U2 SMB connector to measure output voltage. When using this test point, the scope must be set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP26 VO_2NDSTG U2 Test point to measure output voltage after second stage filter if added to EVM.
TP27 PGND Both PGND test point for load transient circuit.
TP29 VOUT_P1 U1 SMB connector to measure output voltage. When using this test point, the scope must be set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP30 VIN_P1 U1 VIN test point. Use this for efficiency measurements.
TP31 VOUT_P1 U1 VOUT test point. Use this for efficiency, output regulation, and bode plot measurements.
TP32 EN_P1 U1 EN test point. If applying an external voltage, then the external voltage must be kept below the absolute maximum voltage of the EN pin of 6 V.
TP33 PGND_P1 U1 PGND test point.
TP34 PGOOD_P1 U1 PGOOD test point.
TP35 AGND_P1 U1 AGND test point.
TP36 PGND_P1 U1 PGND test point. Use this for efficiency measurements.
TP37 VO_SNS U1 Used for Bode plot measurements.
TP38 BODE-_P1 U1 Test point between voltage divider network and output voltage. Used for Bode plot measurements.
TP39 VCC_BUF_P1 U1 VDRV Voltage Supply to Buffer.
TP40 PGND_P1 U1 PGND test point.
TP41 SYNC_P1 U1 SYNC test point. Supply an external clock to this test point to synchronize U4 regulators.