SLUUCJ2C july   2021  – august 2023 UCC14240-Q1 , UCC14241-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 U1 Component Selection
    2. 1.2 Pin Configuration and Functions
  5. 2Description
    1. 2.1 EVM Electrical Performance Specifications
  6. 3Schematic
  7. 4EVM Setup and Operation
    1. 4.1 Recommended Test Equipment
    2. 4.2 External Connections for Easy Evaluation
    3. 4.3 Powering the EVM
      1. 4.3.1 Power on for Start-up
      2. 4.3.2 Power off for Shutdown
    4. 4.4 EVM Test Points
    5. 4.5 Probing the EVM
  8. 5 Performance Data
    1. 5.1  Efficiency Data
    2. 5.2  Regulation Data
    3. 5.3  Steady State Input Current
    4. 5.4  Start-up Waveforms
    5. 5.5  Inrush Current
    6. 5.6  AC Ripple Voltage
    7. 5.7  EN-to-/PG Timing
    8. 5.8  RLIM
    9. 5.9  Fault Protection
      1. 5.9.1 Output UVLO
      2. 5.9.2 Output OVP
    10. 5.10 Shutdown
    11. 5.11 Thermal Performance
  9. 6Assembly and Printed Circuit Board (PCB) Layers
  10. 7Bill of Materials (BOM)
  11. 8Revision History

5.9.2 Output OVP

Figure 5-21 shows the effect of mismatched bias loading at startup where the load on VDD-COM is greater than the load on VEE-COM. A fixed resistive load of 910-Ω (247 mW) is applied to VDD-COM while VEE-COM is left unloaded. VDD-VEE is regulating at 20-V, as expected and VDD-COM is measuring 14.5 V (target value is 15 V) but VEE-COM is measuring 5.5 V (target value is 5 V). VEE-COM is directly monitored by FBVEE and has exceeded 110% of the set target value, triggering OVP and instantly latching both outputs off, regardless of the 16-ms watch-dog-timer. When FBVEE has detected the regulated voltage exceeding the set target value, RLIM is internally switched to VEE, sinking current from the capacitor midpoint, COM connection. When activated, as illustrated in Figure 5-21, the outputs are latched off into a protected sate. EN or VIN must be recycled to clear the OVP fault and attempt to restart the module.

GUID-20221122-SS0I-3RX7-4MQQ-CZZFGGFNF4J8-low.png
top: VDD-VEE, 10 V/div, mid3: VEE-COM, 5 V/div,
mid1: COM-VEE, 5 V/div, bot: RLIM, 20 V/div,
mid2: VDD-COM, 20 V/div, time = 2 ms/div
Figure 5-21 VEE OVP, VIN=24 V, PVDD=247 mW, PVEE = 0 mW

Figure 5-22 shows the same fixed resistive load of 910-Ω (247 mW) applied to VDD-COM as Figure 5-21 but the load on VEE-COM has been increased from 0-mW to 53-mW. Once both outputs are regulating, RLIM is internally connected and held to VEE, sinking current from COM, attempting to compensate for the additional load imbalance present during steady state operation.

GUID-20221122-SS0I-34HP-VKTW-K1NWHXWRCRL7-low.png
top: VDD-VEE, 10 V/div, mid3: VEE-COM, 5 V/div,
mid1: COM-VEE, 5 V/div, bot: RLIM, 20 V/div),
mid2: VDD-COM, 20 V/div, time = 2 ms/div
Figure 5-22 Normal Start, VIN=24 V, PVDD=247 mW, PVEE = 53 mW