SLUUCO5A december 2022 – august 2023 BQ34Z100-R2
An implementation option for HDQ is to use a UART. An advantage to using the UART is that if the UART is handling the communication and storing the results in a buffer, host processor interrupts during the communication do not affect the timing of the HDQ communication with the HDQ target. Use of the UART for HDQ communication requires that each word sent to or received from the UART is only a single bit of the HDQ data or address. The procedure is to set the UART baud rate to 57,600 with no parity and two stop bits. This yields a data word with 11 bits total (start bit, eight data bits, and two stop bits). At a baud rate of 57,600 (17.3 μs per bit), this is a total communication time of 190.9 µs and meets the required HDQ bit timing of 190 µs minimum. If data of 0xFE is sent to the UART, the transmitted data is low for 34.6 µs and then high for the remaining bit time and is interpreted by the HDQ target as a 1. If data of 0xC0 is sent to the UART, the transmitted data is low for 121.5 μs and then high for the remaining bit time and is interpreted by the HDQ target as a 0. When data is sent to the host from the HDQ target, the received data could be interpreted as either 0xFE or 0xFC if a logic 1 is sent, or either 0xF0, 0xE0, 0xC0, 0x80, or 0x00 if a logic 0 is sent. A simple test of the received data determines the received data bit. If the received data is greater than 0xF8, the data bit should be interpreted as a logic 1, and if less than or equal to 0xF8, the data bit should be interpreted as a logic 0. This analysis assumes the UART samples the received data approximately half-way through each of the 17.3-μs UART bit times, and that capacitive loading on the HDQ line may delay the rise time of the data a few microseconds.
Note that the TX and RX of the UART must be tied together because HDQ is a single-wire interface. In case the TX output is not an open-drain output, it needs to be converted to an open-drain output, as shown in Figure 9-5.
Any data sent out to the HDQ target is also received by the UART; therefore, if 8 bits of an address are sent and then 8 bits of data from the HDQ target are received from that address, the UART inputs 16 bytes of data into the UART data buffer. The host needs to skip the first 8 bytes, which contain the command word sent to the HDQ target and use the second 8 bytes of data.