SLUUCO9A April 2023 – November 2023 BQ28Z620
Class | Subclass | Name | Type | Min | Max | Default | Description |
---|---|---|---|---|---|---|---|
Settings | Configuration | FET Options | H1 | 0x00 | 0xFF | 0x20 | Bit 0: Reserved Bit 1: Reserved Bit 2: OTFET—FET action in OVERTEMPERATURE mode 0 = No FET action for overtemperature condition (default) 1 = CHG and DSG FETs will be turned off for overtemperature conditions. Bit 3: CHGSU—FET action in CHARGE SUSPEND mode 0 = FET active (default) 1 = Charging or Precharging disabled, FET off Bit 4: CHGIN—FET action in CHARGE INHIBIT mode 0 = FET active (default) 1 = Charging or Precharging disabled, FET off Bit 5: CHGFET—FET action on valid charge termination 0 = FET active (default) 1 = Charging or Precharging disabled, FET off Bit 6: SLEEPCHG—CHG FET enabled during sleep 0 = CHG FET off during sleep (default) 1 = CHG FET remains on during sleep Bit 7: PMPDRV—FET action in SLEEP mode (Refer to Appendix A.) 0 = AFE gate drive keep at 9.4 V in SLEEP mode (default) 1 = AFE gate drive automatically changes to 5.75 V in SLEEP mode. |
Settings | Configuration | Gauging Configuration | H1 | 0x00 | 0x0F | 0x04 | Bit 0: RSOCL—RelativeStateOfCharge() and RemainingCapacity() behavior at end of charge 0 = Actual value shown (default) 1 = Held at 99% until valid charge termination. On entering valid charge termination update to 100% Bit 1: RSOC_HOLD—Prevent RSOC from increasing during discharge 0 = RSOC not limited 1 = RSOC not allowed to increase during discharge Bit 2: LOCK0—Keep RemainingCapacity() and RelativeStateOfCharge() from jumping back during relaxation after 0 was reached during discharge. 0 = Disabled (default) 1 = Enabled Bit 7:3: Reserved |
Settings | Configuration | I2C Configuration | H1 | 0x00 | 0xFF | 0x01 | Bit 0: BCAST—Enable charging broadcast from device to smart charger 0 = Disabled 1 = Enabled (default) Bit 1: Reserved Bit 2: Reserved Bit 3: XL—Enable 400-kHz COM mode 0 = Normal bus speed (default) 1 = 400-kHz bus speed (slave mode) Bit 5:4: Reserved Bit 6: TO_STRETCH_EN—Enable bus timeouts (15-ms clock high and 25ms clock low) 0 = Disabled (default) 1 = Enabled Bit 7: FLASH_BUSY_WAIT—Enable clock stretching during a flash program or erase operation 0 = Disabled (default) 1 = Enabled |
Settings | Configuration | Power Configuration | H1 | 0x00 | 0x01 | 0x00 | Bit 0: AUTO_SHIP_EN—Automatically
shuts
down for shipment 0 = Disable auto shutdown feature (default) 1 = Enable auto shutdown after device is in SLEEP mode without communication for a set period of time. Bit 3: 1: Reserved Bit 4: SLP_ACCUM—Enable sleep charge accumulation 1 = Enable sleep charge accumulation 0 = Disable sleep charge accumulation (default) Bit 5: SLEEPWKCHG—Enable sleep wake charge feature 1 = Enable sleep wake charge feature 0 = Disable sleep wake charge feature (default) Bit 7: 6: Reserved |
Settings | Configuration | SOC Flag Config A | H2 | 0x0000 | 0xFFFF | 0x0C8C | Bit 0: TDSETV—Enable TD flag set by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 1: TDCLEARV—Enable TD flag clear by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 2: TDSETRSOC—Enable TD flag set by RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 3: TDCLEARRSOC—Enable TD flag clear by RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 4: TCSETV—Enable TC flag set by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 5: TCCLEARV—Enable TC flag clear by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 6: TCSETRSOC—Enable TC flag set by RSOC threshold 0 = Disabled (default) 1 = Enabled Bit 7: TCCLEARRSOC—Enable TC flag clear by RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 8: Reserved Bit 9: Reserved Bit 10: FCSETVCT—Enable FC flag set by primary charge termination 0 = Disabled 1 = Enabled (default) Bit 11: TCSETVCT—Enable TC flag set by primary charge termination 0 = Disabled 1 = Enabled (default) Bit 15: 12: Reserved |
Settings | Configuration | SOC Flag Config B | H1 | 0x0000 | 0x00FF | 0x008C | Bit 0: FDSETV—Enable FD flag set by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 1: FDCLEARV—Enable FD flag clear by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 2: FDSETRSOC—Enable FD flag set by RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 3: FDCLEARRSOC—Enable FD flag clear by RSOC threshold 0 = Disabled 1 = Enabled (default) Bit 4: FCSETV—Enable FC flag set by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 5: FCCLEARV—Enable FC flag clear by cell voltage threshold 0 = Disabled (default) 1 = Enabled Bit 6: FCSETRSOC—Enable FC flag set by RSOC threshold 0 = Disabled (default) 1 = Enabled Bit 7: FCCLEARRSOC—Enable FC flag clear by RSOC threshold 0 = Disabled 1 = Enabled (default) |
Settings | Configuration | Charging Configuration | H1 | 0x00 | 0x3F | 0x00 | Bit 0: CRATE—ChargeCurrent rate 0 = No adjustment to ChargingCurrent() (default) 1 = ChargingCurrent() adjusted based on FullChargeCapacity()/DesignCapacity() Bit 7:1: Reserved |
Settings | Configuration | Temperature Enable | H1 | 0x00 | 0x03 | 0x03 | Bit 0: internal TS— Enable Internal TS 0 = Disable internal TS (default) 1 = Enable internal TS Bit 1: TS1—Enable TS1 0 = Disable TS1 1 = Enable TS1 (default) Bit 7:2: Reserved |
Settings | Configuration | DA Configuration | H1 | 0x00 | 0xFF | 0x11 | Bit 0: CC0—Cell Count 0 = 1 cell 1 = 2 cell Bit 1: Reserved Bit 2: Reserved Bit 3: IN_SYSTEM_SLEEP—In-system SLEEP mode 0 = Disable (default) 1 = Enable Bit 4: SLEEP—SLEEP Mode 0 = Disable SLEEP mode 1 = Enable SLEEP mode (default) Bit 5: Reserved Bit 6: CTEMP—Cell Temperature protection source 0 = MAX (default) 1 = Average Bit 7: Reserved |
Settings | Configuration | IT Gauging Configuration | H2 | 0x0000 | 0xFFFF | 0xD4DE | Bit 0: CCT—Cycle count threshold 0 = Use CC % of DesignCapacity() (default) 1 = Use CC % of FullChargeCapacity() Bit 1: CSYNC—Sync RemainingCapacity() with FullChargeCapacity() at valid charge termination 0 = Not synchronized 1 = Synchronized (default) Bit 2: RFACTSTEP—Allow Ra update to limit before disqualifying further updates 0 = If (new Ra)/(old Ra) > 3, Ra update is not completed, and Ra updates are disabled. 1 = If (new Ra)/(old Ra) > 3, one Ra update is completed limited to factor of 3, and further Ra updates are disabled. Bit 3: OCVFR—Open Circuit Voltage Flat Region 0 = Disabled 1 = Enabled (default) Bit 4: Reserved Bit 5: Reserved Bit 6: RSOC_CONV—See Section 8.6. Bit 7: FAST_QMax_LRN—See Section 8.6. Bit 8: FAST_Qmax_FLD—See Section 8.6. Bit 9: CELL_TERM—See Section 8.6. Bit 10: FF_NEAR_EDV—See Section 8.6. Bit 11: RELAX_JUMP_OK—See Section 8.6 Bit 12: SMOOTH—See Section 8.6. Bit 13: Reserved Bit 14: Reserved Bit 15: SYNC_AT_OCV—See Section 8.6. |
Settings | Configuration | Balancing Configuration | H1 | 0x00 | 0xFF | 0x01 | Bit 0: CB—Cell balancing 0 = Cell balancing disabled 1 = Cell balancing enabled (default) Bit 1: Reserved Bit 2: CBR—Cell balancing at rest 0 = Cell balancing at rest is disabled (default). 1 = Cell balancing at rest is enabled. Bit 7:3: Reserved |