SLUUCP8 June 2024 BQ41Z50
This command returns the PFAlert() flags on ManufacturerBlockAccess() or ManufacturerData().
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TS4 | TS3 | TS2 | TS1 | TMPC | RSVD | RSVD | RSVD | RSVD | 2LVL | AFEC | AFER | FUSE | OCDL | DFE TF | CFE TF |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASC DL | ASC CL | AOL DL | VIMA | VIMR | CD | IMP | CB | QIM | SOTF | COVL | SOT | SOCD | SOCC | SOV | SUV |
TS4 (Bit 31): Open thermistor–TS4 failure | ||
1 = | Detected | |
0 = | Not detected | |
TS3 (Bit 30): Open thermistor–TS3 failure | ||
1 = | Detected | |
0 = | Not detected | |
TS2 (Bit 29): Open thermistor–TS2 failure | ||
1 = | Detected | |
0 = | Not detected | |
TS1 (Bit 28): Open thermistor–TS1 Failure | ||
1 = | Detected | |
0 = | Not detected | |
TMPC (Bit 27): TMP468 Communication Failure | ||
1 = | Detected | |
0 = | Not detected | |
RSVD (Bits 26–23): Reserved. Do not use. | ||
2LVL (Bit 22): Second level protector failure | ||
1 = | Detected | |
0 = | Not detected | |
AFEC (Bit 21): AFE communication failure | ||
1 = | Detected | |
0 = | Not detected | |
AFER (Bit 20): AFE register failure | ||
1 = | Detected | |
0 = | Not detected | |
FUSE (Bit 19): Chemical fuse failure | ||
1 = | Detected | |
0 = | Not detected | |
OCDL (Bit 18): Overcurrent in discharge | ||
1 = | Detected | |
0 = | Not detected | |
DFETF (Bit 17): Discharge FET failure | ||
1 = | Detected | |
0 = | Not detected | |
CFETF (Bit 16): Charge FET failure | ||
1 = | Detected | |
0 = | Not detected | |
ASCDL (Bit 15): Short circuit in discharge | ||
1 = | Detected | |
0 = | Not detected | |
ASCCL (Bit 14): Short circuit in charge | ||
1 = | Detected | |
0 = | Not detected | |
AOLDL (Bit 13): Overload in discharge | ||
1 = | Detected | |
0 = | Not detected | |
VIMA (Bit 12): Voltage imbalance while pack is active failure | ||
1 = | Detected | |
0 = | Not detected | |
VIMR (Bit 11): Voltage imbalance while pack is at rest failure | ||
1 = | Detected | |
0 = | Not detected | |
CD (Bit 10): Capacity degradation failure | ||
1 = | Detected | |
0 = | Not detected | |
IMP (Bit 9): Impedance failure | ||
1 = | Detected | |
0 = | Not detected | |
CB (Bit 8): Cell balancing failure | ||
1 = | Detected | |
0 = | Not detected | |
QIM (Bit 7): QMax imbalance failure | ||
1 = | Detected | |
0 = | Not detected | |
SOTF (Bit 6): Safety overtemperature FET failure | ||
1 = | Detected | |
0 = | Not detected | |
COVL (Bit 5): Cell overvoltage latch | ||
1 = | Detected | |
0 = | Not detected | |
SOT (Bit 4): Safety overtemperature cell failure | ||
1 = | Detected | |
0 = | Not detected | |
SOCD (Bit 3): Safety overcurrent in discharge | ||
1 = | Detected | |
0 = | Not detected | |
SOCC (Bit 2): Safety overcurrent in charge | ||
1 = | Detected | |
0 = | Not detected | |
SOV (Bit 1): Safety cell overvoltage failure | ||
1 = | Detected | |
0 = | Not detected | |
SUV (Bit 0): Safety cell undervoltage failure | ||
1 = | Detected | |
0 = | Not detected |