SLUUCP8 June 2024 BQ41Z50
Class | Subclass | Name | Type | Min | Max | Default | Unit |
---|---|---|---|---|---|---|---|
Settings | Permanent Failure | Enabled PF D | H1 | 0x00 | 0xFF | 0x00 | Hex |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS4 | TS3 | TS2 | TS1 | RSVD | RSVD | FORCE | RSVD |
TS4 (Bit 7) | ||
1 = | Enabled (default) | |
0 = | Disabled | |
TS3 (Bit 6) | ||
1 = | Enabled (default) | |
0 = | Disabled | |
TS2 (Bit 5) | ||
1 = | Enabled (default) | |
0 = | Disabled | |
TS1 (Bit 4) | ||
1 = | Enabled (default) | |
0 = | Disabled | |
RSVD (Bits 3–2): Reserved. Do not use. | ||
FORCE (Bit 1): Manual PF. See Manual Permanent Failure for more information. | ||
1 = | Enabled (default) | |
0 = | Disabled | |
RSVD (Bit 0): Reserved. Do not use. |