SLUUCP8 June 2024 BQ41Z50
The BQ41Z50 device has three main hardware-based protections—AOLD, ASCC, and ASCD1,2—with adjustable current and delay time. Setting AFE Protection Configuration[RSNS] divides the threshold value in half. The Threshold settings are in mV; therefore, the actual current that triggers the protection is based on the RSENSE used in the schematic design.
In addition, setting the AFE Protection Configuration[SCDDx2] bit provides an option to double all of the SCD1,2 delay times for maximum flexibility towards the application's needs.
For details on how to configure the AFE hardware protection, refer to the tables in Appendix A.
All of the hardware-based protections provide a Trip/Latch Alert/Recovery protection. The latch feature stops the FETs from toggling on and off continuously on a persistent faulty condition.
In general, when a fault is detected after the Delay time, the CHG and DSG FETs will be disabled (Trip stage), and an internal fault counter will be incremented (Alert stage). Since both FETs are off, the current will drop to 0 mA. After Recovery time, the CHG and DSG FETs will be turned on again (Recovery stage).
If the alert is caused by a current spike, the fault count will be decremented after Counter Dec Delay time. If this is a persistent faulty condition, the device will enter the Trip stage after Delay time, and repeat the Trip/Latch Alert/Recovery cycle. The internal fault counter is incremented every time the device goes through the Trip/Latch Alert/Recovery cycle. Once the internal fault counter hits the Latch Limit, the protection enters a Latch stage and the fault will only be cleared through the Latch Reset condition.
The Trip/Latch Alert/Recovery/Latch stages are documented in each of the following hardware-based protection sections.
The recovery condition for the removable pack ([NR] = 0) is based on the transition on the PRES pin, while the recovery condition for the embedded pack ([NR] = 1) is based on the Reset time.