|
NTC
(Bit 7): Permanent Fail Flag Display |
| 1 = | Enables
PFStatus[NTC]
= 1 when
NTC
fault is triggered.
|
| 0 = | Disables the
PFStatus[NTC]
= 1 when
NTC
fault is triggered.
|
| | |
2LVL (Bit 6): FUSE input indicating a fuse trigger by an external 2nd-level protection |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
AFEC (Bit 5): AFE Communication |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
AFER (Bit 4): AFE Register |
| 1 = | Enabled |
| 0 = | n/a (default) |
| | |
FUSE (Bit 3): Fuse |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
OCDL (Bit 2): Overcurrent in Discharge—PF Enable |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
DFETF (Bit 1): Discharge FET |
| 1 = | Enabled |
| 0 = | Disabled (default) |
| | |
CFETF (Bit 0): Charge FET |
| 1 = | Enabled |
| 0 = | Disabled (default) |