SLUUCR7A January   2023  – December 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Warning and Caution
  5. 2Introduction
    1. 2.1 Performance Specification
    2. 2.2 Dual Package Layout
    3. 2.3 Modifications
      1. 2.3.1 Input and Output Capacitors
      2. 2.3.2 Loop Response Measurement
  6. 3Setup
    1. 3.1 Connector Descriptions
    2. 3.2 Hardware Setup
  7. 4TPS62830xRZEREVM Test Results
  8. 5Board Layout
  9. 6Schematic and Bill of Materials
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
  10. 7Revision History

Board Layout

This section provides the TPS62830xRZEREVM board layout and illustrations in Figure 5-1 through Figure 5-6.

GUID-20230110-SS0I-D6L1-4R6K-VPD1QCVLHDXK-low.svg Figure 5-1 Top Assembly
GUID-20230110-SS0I-L7KS-KGFR-FZJM3Z4T0HQP-low.svg Figure 5-2 Top Layer
GUID-20230110-SS0I-7JGV-NJGT-WFMVH3DMQWRX-low.svg Figure 5-3 Signal Layer 1
GUID-20230110-SS0I-1SLK-0WLP-TSZFDPXBMMSL-low.svg Figure 5-4 Signal Layer 2
GUID-20230110-SS0I-1FBQ-ZQ8Z-BVJZZ09TWBZX-low.svg Figure 5-5 Bottom Layer
GUID-20230110-SS0I-RXRH-8GFG-HLLFJHGHSZHZ-low.svg Figure 5-6 Bottom Assembly