SLUUCW8 October 2023 BQ27Z746
Class | Subclass | Name | Type | Min | Max | Default | Unit |
---|---|---|---|---|---|---|---|
Settings | Permanent Failure | Enabled PF A | H2 | 0x00 | 0xFF | 0x00 | Hex |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | RSVD | RSVD | RSVD | RSVD | RSVD | SOV | SUV |
RSVD (Bit 7-2): Reserved. Do not use. | ||
SOV (Bit 1): Safety Cell Overvoltage | ||
1 = | Enabled | |
0 = | Disabled (default) | |
SUV (Bit 0): Safety Cell Undervoltage | ||
1 = | Enabled | |
0 = | Disabled (default) |
Class | Subclass | Name | Type | Min | Max | Default | Unit |
---|---|---|---|---|---|---|---|
Settings | Permanent Failure | Enabled PF C | H2 | 0x00 | 0xFF | 0x00 | Hex |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | RSVD | RSVD | RSVD | RSVD | RSVD | DFETF | CFETF |
RSVD (Bit 7-2): Reserved. Do not use. | ||
CFETF (Bit 1): Discharge Fet Failure |
||
1 = | Enabled | |
0 = |
Disabled (default) |
|
DFETF (Bit 0): Charge Fet Failure |
||
1 = | Enabled | |
0 = |
Disabled (default) |