15 | SSBC | Setting this bit causes the Alarm Status()[SSBC] to be set
and latched when Alarm Raw Status()[SSBC] is
asserted. |
14 | SSA | Setting this bit causes the Alarm Status()[SSA] to be set
and latched when Alarm Raw Status()[SSA] is asserted. |
13 | PF | Setting this bit causes the Alarm Status()[PF] to be set
and latched when Alarm Raw Status()[PF] is asserted. |
12 | MSK_SFALERT | Setting this bit causes the Alarm Status()[MSK_SFALERT] to
be set and latched when Alarm Raw Status()[MSK_SFALERT] is
asserted. |
11 | MSK_PFALERT | Setting this bit causes the Alarm Status()[MSK_PFALERT] to
be set and latched when Alarm Raw Status()[MSK_PFALERT] is
asserted. |
10 | INITSTART | Setting this bit causes the Alarm Status()[INITSTART] to
be set and latched when Alarm Raw Status()[INITSTART] is
asserted. |
9 | INITCOMP | Setting this bit causes the Alarm Status()[INITCOMP] to be
set and latched when Alarm Raw Status()[INITCOMP] is
asserted. |
7 | FULLSCAN | Setting this bit causes the Alarm Status()[FULLSCAN] to be
set and latched when Alarm Raw Status()[FULLSCAN] is
asserted. |
6 | XCHG | Setting this bit causes the Alarm Status()[XCHG] to be set
and latched when Alarm Raw Status()[XCHG] is
asserted. |
5 | XDSG | Setting this bit causes the Alarm Status()[XDSG] to be set
and latched when Alarm Raw Status()[XDSG] is
asserted. |
4 | SHUTV | Setting this bit causes the Alarm Status()[SHUTV] to be
set and latched when Alarm Raw Status()[SHUTV] is
asserted. |
3 | FUSE | Setting this bit causes the Alarm Status()[FUSE] to be set
and latched when Alarm Raw Status()[FUSE] is
asserted. |
2 | CB | Setting this bit causes the Alarm Status()[CB] to be set
and latched when Alarm Raw Status()[CB] is asserted. |
1 | ADSCAN | Setting this bit causes the Alarm Status()[ADSCAN] to be
set and latched when Alarm Raw Status()[ADSCAN] is
asserted. |
0 | WAKE | Setting this bit causes the Alarm Status()[WAKE] to be set
and latched when Alarm Raw Status()[WAKE] is
asserted. |