SLUUCX4 august   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Input and Output Connections
    2. 2.2 Modifications
      1. 2.2.1 Output Voltage Setpoint
      2. 2.2.2 Mode Selection
  8. 3Implementation Results
    1. 3.1 Evaluation Setup
    2. 3.2 Test Setup and Results
      1. 3.2.1 Start-Up
      2. 3.2.2 Shutdown
      3. 3.2.3 Output Voltage Ripple
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  10. 5Additional Information
    1.     Trademarks
  11. 6References

PCB Layout

The following figures show the board layout for the TPS568236EVM. TPS568236EVM is with four layers. The top layer contains the main power traces for VIN, VOUT, and GND. Also on the top layer are connections for the pins of the TPS568236 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors C4, C5, and C6 are located as close to VIN pins and PGND pins of the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with signal ground copper fill and the feedback trace from the point of regulation to the top of the resistor divider network. Two inner layers are ground plane.

GUID-20230804-SS0I-LHNS-M2BZ-J4JBSZ71DJGM-low.svgFigure 4-2 Top Assembly
GUID-20230804-SS0I-GHBS-Z22Q-KMPS3Q3CCJK0-low.svgFigure 4-3 Top Layer
GUID-20230804-SS0I-SMZ8-RHPJ-8VFMSLQ6FHJ3-low.svgFigure 4-4 Inner1 Layer
GUID-20230804-SS0I-RJC3-GZVB-NXKZDZWM5RJQ-low.svgFigure 4-5 Inner2 Layer
GUID-20230804-SS0I-HJVK-KJLX-DJKMSSS86ZPW-low.svgFigure 4-6 Bottom Layer