This section provides a description of the TPSM86125xEVM, board layout, and layer illustrations.

Figure 5-2, Figure 5-3, Figure 5-4, Figure 5-5, and Figure 5-6 show the board layout for the TPSM861253EVM. The top layer contains the main power traces for VIN, VOUT, and ground. Connections for the pins of the TPSM861253 and a large area filled with ground are also on the top layer. Most of the signal traces are also located on the top side. The input decoupling capacitors C1 and C2 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the signal ground copper fill and the feedback trace from the point of regulation to the top of the resistor divider network. Two internal layers are both set to ground plane. Both the top layer and bottom layer use 2-oz copper thickness and two internal layers use 1-oz copper thickness.

Figure 4-2 TPSM861253EVM Top Assembly

Figure 4-3 TPSM861253EVM Top Layer

Figure 4-4 TPSM861253EVM Inner1 Layer

Figure 4-5 TPSM861253EVM Inner2 Layer

Figure 4-6 TPSM861253EVM Bottom Layer