SLUUD24 May   2024 BQ25770G

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 General Description
    2. 2.2 Definitions
    3. 2.3 Equipment
    4. 2.4 Equipment Setup
    5. 2.5 Procedure
      1. 2.5.1 Charge Function
      2. 2.5.2 OTG Function
  9. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks

2.1 General Description

The NVDC configuration allows the system to be regulated at the battery voltage, but does not drop below the system minimum voltage. The system keeps operating even when the battery is completely discharged or removed. When load power exceeds the input source rating, the battery supplement mode prevents the input source from being overloaded.

During power up, the charger sets the converter to buck, boost, or buck-boost configuration based on the input source and battery conditions. During the charging cycle, the charger automatically transits among buck, boost, and buck-boost configuration without host control.

The BQ2577xG monitors adapter current, battery current, and system power. The flexibly programmed PROCHOT output goes directly to the CPU for throttle back, when needed.

For more details, please see the BQ2577xG: 40V, SMBus or I2C, 2- to 5-Cell, Narrow VDC Dual Phase Buck-Boost Battery Charge Controller for GaN HEMT With System Power Monitor and Processor Hot Monitor data sheet.

Table 3-1 lists the I/O descriptions.

Table 2-1 I/O Description
JackDescription
J1–VINInput: positive terminal
J1–PGNDInput: negative terminal (ground terminal)
J2-VSYSConnected to system output
J2-PGNDGround
J3-VBATConnected to battery pack output
J3-PGNDGround
J4-EXT5VConnected to external 5V supply
J4-PGNDGround
J5-ILIM_HIZExternal converter disable
J5-CHRG_OKCHRG_OK output
J5-EN_OTGExternal OTG enable pin
J5-CELL_controlExternal battery removal control; logic high to pull the CELL pin down
J6–3V3Onboard 3.3V output
J6–SDASMBUS or I2C SDA
J6-SCLSMBUS or I2C SCL
J6-GNDGround

J8–SDA

SMBUS or I2C SDA
J8-SCLSMBUS or I2C SCL
J8-GNDGround

Table 3-2 displays the controls and key parameters settings.

Table 2-2 Controls and Key Parameters Setting
JumperDescriptionFactory Setting
JP1Jumper on: Bat removal
Jumper off: Cell setting by JP4		Not installed
JP2Jumper on: Forward Mode
Jumper off: OTG Mode		Installed
JP3For input current setting:
Jumper on: Enter HiZ mode.
Jumper off: Allow pre-bias EXTLIM		Not installed
JP4CELL setting:
2S: JP4(1-2), measure CELL pin voltage 2V
3S: JP4(3-4), measure CELL pin voltage 2.75V
4S: JP4(5-6), measure CELL pin voltage 3.76V
5S: JP4(7-8), measure CELL pin voltage 5V		4S setting: JP4(5-6)
JP5Jumper on: Onboard 3.3V LDO enabled
Jumper off: Disconnect onboard 3.3V LDO		Installed