SLVA469D June   2013  – January 2023 TLV62130 , TLV62130A , TLV62150 , TLV62150A , TPS61175 , TPS61175-Q1 , TPS62130 , TPS62130A , TPS62131 , TPS62132 , TPS62133 , TPS62135 , TPS62136 , TPS62140 , TPS62140A , TPS62141 , TPS62142 , TPS62143 , TPS62150 , TPS62150A , TPS62151 , TPS62152 , TPS62153 , TPS62160 , TPS62161 , TPS62162 , TPS62163 , TPS62170 , TPS62171 , TPS62172 , TPS62173

 

  1.   Using the TPS6215x in an Inverting Buck-Boost Topology
  2.   Trademarks
  3. 1Inverting Buck-Boost Topology
    1. 1.1 Concept
    2. 1.2 Output Current Calculations
    3. 1.3 VIN and VOUT Range
  4. 2Design Considerations
    1. 2.1 Design Precautions
    2. 2.2 Additional Input Capacitor
    3. 2.3 Digital Pin Configurations
      1. 2.3.1 Digital Input Pins (EN, FSW, DEF)
      2. 2.3.2 Power Good Pin
    4. 2.4 Startup Behavior and Switching Node Consideration
  5. 3External Component Selection
    1. 3.1 Inductor Selection
    2. 3.2 Capacitor Selection
  6. 4Typical Performance
  7. 5Conclusion
  8. 6References
  9. 7Revision History

2.4 Startup Behavior and Switching Node Consideration

In the inverting buck-boost topology, the voltage on the SW pin switches from VIN to VOUT, instead of from VIN to GND. As the high-side MOSFET turns on, the SW node sees the input voltage; as the low-side MOSFET turns on, the SW node sees the device ground, which is the output voltage. During startup, VIN rises to achieve the desired input voltage. VOUT starts ramping down after the EN pin voltage exceeds its threshold level and VIN exceeds its UVLO threshold. As VOUT continues to ramp down, the SW node low level follows it down. Figure 2-10 shows the resulting normal and smooth startup of the output voltage.

GUID-8C845C76-6DB4-406C-A8DF-6DF2A0AB84D6-low.gif Figure 2-10 SW Node Voltage During Startup