SLVA528D September   2012  – August 2021 TPS65381-Q1 , TPS65381A-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Product Overview
    1. 2.1 Safety Functions and Diagnostics Overview
    2. 2.2 Target Applications
    3. 2.3 Product Safety Constraints
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
  5. 4TPS65381x-Q1 Product Architecture for Management of Random Faults
    1. 4.1 Device Operating States
    2.     Device Operating States (continued)
    3. 4.2 NRES (MCU Reset) Driver and ENDRV (SAFING Path Enable) Driver
  6. 5TPS65381x-Q1 Architecture Safety Mechanisms and Assumptions of Use
    1. 5.1 Power Supply
    2. 5.2 Regulated Supplies
      1. 5.2.1 VDD6 Buck Switch-Mode Supply
      2. 5.2.2 VDD5 Linear Supply
      3. 5.2.3 VDD3/5 Linear Supply
      4. 5.2.4 VDD1 Linear Supply
      5. 5.2.5 VSOUT1 Linear Supply
      6. 5.2.6 Charge Pump
    3. 5.3 Diagnostic, Monitoring, and Protection Functions
      1. 5.3.1 External MCU Fault Detection and Management
        1. 5.3.1.1 External MCU Error Signal Monitor (MCU ESM)
        2. 5.3.1.2 Watchdog Timer
      2. 5.3.2 Voltage Monitor (VMON)
      3. 5.3.3 Loss-of-Clock Monitor (LCMON)
      4. 5.3.4 Junction Temperature Monitoring and Current Limiting
      5. 5.3.5 Analog and Digital MUX (AMUX and DMUX) and Diagnostic Output Pin (DIAG_OUT)
      6. 5.3.6 Analog Built-In Self-Test (ABIST)
      7. 5.3.7 Logic Built-In Self-Test (LBIST)
      8. 5.3.8 Device Configuration Register Protection
  7. 6Application Diagrams
    1. 6.1 TPS65381x-Q1 With TMS570
    2. 6.2 TPS65381x-Q1 With C2000
    3. 6.3 TPS65381x-Q1 With TMS470
  8. 7TPS65381x-Q1 as Safety Element out of Context (SEooC)
    1. 7.1 TPS65381x-Q1 Used in an EV/HEV Inverter System
    2. 7.2 SPI Note
  9. 8Revision History

5.2.4 VDD1 Linear Supply

Use of an external power NMOS reduces the on-chip power consumption. Limiting the VDD1 gate output prevents gate-source overvoltage stress during power up or during line or load transients.

The VDD1 LDO controller does not have a current limit or overtemperature protection for the external NMOS FET. Therefore, TI recommends supplying the VDD1 LDO controller from VDD6 the regulator. VDD6 current limit acts as a current limit for the VDD1 LDO controller and also limits the power dissipation.

If the VDD1 regulator is not being used, leave the VDD1_G and VDD1_SENSE pins open. An internal pullup device on the VDD1_SENSE pin detects the open connection and pulls up the VDD1_SENSE pin. This forces the regulation loop to bring the VDD1_G output down. This mechanism also masks the VDD1_OV flag in the VMON_STAT_2 register and therefore ENDRV pin action from a VDD1 OV condition is also masked. These actions are equivalent to clearing the NMASK_VDD1_UV_OV bit in the DEV_CFG1 register to 0. This internal pullup device on the VDD1_SENSE pin also prevents a real VDD1 overvoltage on the MCU core supply in case of an open connection to the VDD1_SENSE pin, as it brings the VDD1_G pin down. Therefore, in this situation, the VDD1 output voltage is 0 V.

The internal pullup for the VDD1_SENSE pin also prevents a VDD1 overvoltage on the MCU core supply in case of an open connection in the feedback network, because it brings the VDD1_G pin low. So in this situation, the VDD1 output voltage is 0 V.

Note:

The following cases must be considered with respect to the VDD1 linear supply, assuming a typical application where the VDD1 regulator is supplied from the VDD6 preregulator.

In a fault case, if the VDD1_G pin (pin 26) is shorted to the VDD6 pin (pin 27), the VDD1_G pin is pulled up to VDD6. The VDD1 regulator output voltage will increase to VDD6. The resulting overvoltage on VDD1 will not be detected because the overvoltage on VDD1 pulls the VDD1_SENSE pin higher than the threshold for the floating pin detection on the VDD1_SENSE pin. No impact occurs to the ENDRV pin level, device state, or NRES pin level.

In a fault case, if the VDD1_SENSE (pin 24) is shorted to ground or the GND (pin 23) or the PGND (pin 25), the VDD1_G output voltage increases to its maximum output voltage. The VDD1 regulator output increases to VDD6. If the NMASK_VDD1_UV_OV bit is cleared to 0 (default), the resulting overvoltage on VDD1 and undervoltage on VDD1_SENSE is masked so no impact occurs to the device operation. If the NMASK_VDD1_UV_OV bit is set to 1, the device will detect an undervoltage on the VDD1_SENSE pin causing a transition to RESET state which drives the NRES pin low and the ENDRV pin low.