SLVAE11A August 2018 – January 2021 TPS65987D , TPS65988

2 TPS65987D GPIO Event List

TPS65987D firmware implements specific events that can be tied to GPIOs. These assigned events dictate the behavior of a system in response to a defined hardware or USB event. The TPS6598x Application Customization tool can be used to assign events to specific GPIOs. Table 2-1 lists all the GPIO events that are available in TPS65987D and their behavior.

Table 2-1 List of TPS65987D GPIO Events

Event Name	I/O	Active State	Behavior
Port 0 Plug Event	Output	High	Asserted high when plug event (attached state) has occurred. Asserted low when disconnected.
Port 0 Cable Orientation Event	Output	High	Asserted high when plug is connected upside-down. Asserted low when the plug is connected upside-up or disconnected.
Port 0 AMSEL Event	Output	N/A(Tri-state)	Asserted high when DisplayPort alternate mode is entered and pin assignment A/C/E. Asserted low when DisplayPort alternate mode is entered and pin assignment B/D/F. High-Z when DisplayPort alternate mode is not entered.
Port 0 Source PDO 0 Negotiated Port 0 Source PDO 1 Negotiated Port 0 Source PDO 2 Negotiated Port 0 Source PDO 3 Negotiated	Output	High	Asserted high when source PDO x has been negotiated, otherwise low.
Port 0 Source PDO Negotiated TT 1 Port 0 Source PDO Negotiated TT 2 Port 0 Source PDO Negotiated TT 3	Input	High	These 3 Events combine to form a 3-bit truth table to allow digital outputs indicating the active state of up to 7 PDOs. TT 3 is the most-significant bit (MSB) and TT 1 is the least significant bit (LSB).
Output Enabled Without Event	Output	N/A	Acting as an output without any event.
Port 0 PDIO In 0 Event Port 0 PDIO In 1 Event Port 0 PDIO In 2 Event Port 0 PDIO In 3 Event	Input	N/A	Input GPIO event for PDIO Alternate Mode (when supported by both port partners and mode is entered). A change in state of PDIO In x will trigger a PDIO Alternate Mode message to be sent to the port partner. PDIO Out x will reflect the value of this signal after the PDIO Alternate Mode message is received by the port partner. These events do not have a pre-determined active state.
Port 0 PDIO Out 0 Event Port 0 PDIO Out 1 Event Port 0 PDIO Out 2 Event Port 0 PDIO Out 3 Event	Output	N/A	Output GPIO event for PDIO Alternate Mode. When PDIO Alternate Mode is supported by both port partners and entered, output follows GPIO pin mapped to PDIO In x event on port partner.
Port 0 USB3 Event	Output	High Z	High-Z when data connection is USB3 on Port 0, low in all other cases.
Port 0 DP Mode Select Event	Output	High	Asserted high when data connection is DisplayPort (either 4-Lane mode or 2- Lane+USB3 mode). Asserted low when Type-C port is disconnected or DisplayPort mode is not active.
Port 0 User SVID Active Event	Output	High	Asserted high when port is in User SVID Alternate Mode, otherwise low.
Port 0 Source Sink Event	Output	N/A(Tri-state)	Asserted high when port is operating as a Source. Asserted low when port is operating as a Sink.
Port 0 DP or USB3 Event	Output	High	Asserted high when data connection is DisplayPort or USB3. Asserted low if neither data mode is active or port is disconnected.
Port 0 UFP DFP Event	Output	High	Asserted high when port is operating as UFP. Asserted low when port is operating as DFP.
Port 0 TBT Event	Output	High	Asserted high when data connection is thunderbolt otherwise low.
Port 0 Billboard Event	Output	High	Asserted high when Billboard is presented, otherwise low.
Port 0 Fault Input Event	Input	Low	Used to allow external devices to enable error recovery on a given port. There is one fault condition input per port. When set low port enters Error Recovery State. When set high, no action.
Port 0 FRSwap Input Event	Input	N/A	On the falling edge of input event, a device configured as a Source will enable the FRS pulldown on the CC pin and start the FRS process. No action on rising edge of input event.
Port 0 Fault_Condition_Active_Low_ Event	Output	Low	Asserts low on an overcurrent event.
Port 0 Load App Config 1 Event Port 0 Load App Config 2 Event Port 0 Load App Config 3 Event	Input	N/A	Upon Rising Edge: App Config Set for GPIO = High will be loaded as the active configuration. 1st 4CC Data and Command is written to selected CMDX register (optional). 2nd 4CC Data and Command (or PD Task) is written to selected CMDX register (optional).
	Input	N/A	Upon Falling Edge: App Config Set for GPIO = Low will be loaded as the active configuration. 1st 4CC Data and Command is written to selected CMDX register (optional). 2nd 4CC Data and Command (or PD Task) is written to selected CMDX register (optional).
Port 0 Sink Greater Than Threshold Event	Output	High	Asserted high when in an active PD contract and Sinking less than threshold setting. Asserted low when any other sink or source PD contract is active, no PD contract is active, or port is disconnected.
Port 0 Retimer_PWR_EN_Event	Output	High	Asserted high when USB Type-C connection is present, or when the "Retimer_SoC_Force_PWR_Event" is asserted high. Otherwise, this event is asserted low.
Port 0 Retimer_Reset_N_Event	Output	High	Asserted high when a USB Type-C connection is present and asserted low when there is no USB Type-C connection present. Upon a USB Type-C connection, first the "Retimer_PWR_EN_Event_Portx" event will occur, and then this event will occur tRetimerForcePowerDelay later. When a USB Type-C connection is removed, first this event will go low, and then "Retimer_PWR_EN_Event_Portx" event will happen tRetimerForcePowerDelay later. tRetimerForcePowerDelay is set in the 0x43 Delay Configuration Register.
Port 0 Prochot N Event	Output	High	A signal to the main SOC to notify it of any changes in power capabilities. When this event is asserted, typically the main SOC will reduce its power consumption until it has re-evaluated the new power capabilities of the system. This event is asserted high when the device enters Unattached.SRC, Unattached.SNK, when sending a Request message, sending an Accept message to a PR_SWAP request, or when a PD3.0 Fast Role Swap occurs. This event is asserted low when the ProcHot interrupt in the IntEventX register (0x14 for port 1, 0x15 for port 2) is cleared.
Retimer SOC OVR Force Power Event	Input	High	When this input is asserted (high), the PD controller (through the Retimer_PWR_EN_Event_Portx GPIO event) will instruct the external retimers to power on always, even when no USB Type-C connection is present. When this input is deasserted (low), the PD controller will only instruct the external retimers to power on when a USB Type-C connection is present.
Barrel Jack Detect Event	Input	High	Upon Rising Edge (Barrel Jack detected): Clear Dead Battery Flag Set Externally Powered = 1 Swap to Source
Barrel Jack Detect Event	Input	High	Upon Falling Edge (Barrel Jack removed): Set Externally Powered = 0 Swap to Sink
UFP Indicator Event	Output	High	Asserted high when at least one port has a data role of UFP, otherwise low.
Prevent DR Swap to UFP_Event	Input	High	When high DR_Swap requests that would result in the target port changing to the UFP role will be rejected.
High Current Contract Active Event	Output	High	Asserted high when at least one port has negotiated a source contract exceeding 5 V at 0.9 A, otherwise low.
Prevent High Current Contract Active Event	Input	High	When high source capabilities are reduced to only 5 V at 0.9 A.
Port 0 Audio Mode Event	Output	High	This event is asserted when an Audio Accessory (Ra/Ra) is attached.
Port 0 Source Power Greater Than Threshold	Output	High	This event is asserted high when the USB Type-C implicit contract of the explicit USB PD contract currently negotiated is allowing the sourcing of power greater than the threshold value programmed in the PowerThresAsSourceContract Byte 7 in the Port Configuration Register (0x28). Asserted low when the currently negotiated contract is less than the programmed threshold.
Port 0 Debug Accessory Event	Output	High	Asserted high when debug accessory mode is detected, otherwise low.
Port 0 Sink PDO 0 Negotiated Port 0 Sink PDO 1 Negotiated Port 0 Sink PDO 2 Negotiated Port 0 Sink PDO 3 Negotiated	Output	High	This event is asserted when the TXSinkPDO1 from the TX Sink Capabilities Register (0x33) has been negotiated. Otherwise, this event is deasserted.
Port 0 Sink PDO Negotiated TT 1 Port 0 Sink PDO Negotiated TT 2 Port 0 Sink PDO Negotiated TT 3	Input	High	These 3 Events combine to form a 3-bit truth table to allow digital outputs indicating the active state of up to 7 PDOs. TT 3 is the most-significant bit (MSB) and TT 1 is the least significant bit (LSB).
Port 0 Vconn On	Output	High	Asserted high when PP_CABLE1 is enabled to source VCONN.
Disabled	N/A	N/A	GPIO is disabled.
Port 0 PR_Swap_Ext_Vbus_Dsch	Output	Low	This event causes the mapped GPIO to be pulled low after a PR_Swap to enable an external VBUS discharge circuit during a power-role swap on port 0
PP1 Switch Event	Output	High	Asserted high when PP1 switch is closed. Asserted low when PP1 switch opens.
Port 0 I2C1 Master IRQ Event	Input	High	When this input is asserted, it generates an interrupt to the I2C1 master so it can properly respond to an external retimer.
Port 0 I2C3 Master IRQ Event	Input	High	When this input is asserted, it generates an interrupt to the I2C3 master so it can properly respond to an external retimer.
Port 0 USB2 on HS MUX Event	Output	High	Asserted high when USB2 is active, otherwise low.
Port 0 BC1.2_Host_Pull_Down_Enable_Event	Output	Low	This event is set low when BC1.2 ChargerAdvertiseEnable bits are set to one of the DCP modes in the Port Control Register (0x29) to disable the USB2.0 Host Pulldowns (Hi-Z them), if the USB Host needs an external signal to disable its pulldowns, so the BC1.2 DCP modes can function properly. This event is also asserted low when there is no USB Type-C connection. Otherwise, it is asserted high.
Sink Arbitration GPIO Output	Output	High	Works in conjunction with Sink_Arbitration_Input to ensure only one sinking path in the system is turned on.
Sink Arbitration GPIO Input	Input	High	On a falling edge of this GPIO, the PD controller will evaluate the policy engine state and context for each port. If appropriate, the PD controller will enable the sink paths for one or both ports. Before enabling the sink paths, the Sink_Arbitration_Output will be driven high, and the PD controller will wait for the MultiPortSinkNonOverlapTime which is set in the Global System Configuration register (0x27). On a rising edge of this GPIO, the PD controller disables the sink paths for the ports that are connected to a USB PD source The PD controller also drives the Sink_Arbitration_Output low.