The power-distribution switch family is intended for applications such as USB where heavy capacitive loads and short circuits are likely to be encountered. Device features include enable, reverse blocking when disabled, output discharge pulling down, over-current protection, over temperature protection, and de-glitch fault reporting.

The open-drain output fault signal asserts as over current and over temperature conditions encountered with about 9 ms de-glitch time.

However, as the device is powered up in a fast slew rate, the fault signal falsely asserts that lead to the incorrect operation of the System-on-Chip (SoC). Figure 1-1 shows the set-up of the bench and ramp V_IN at 6 V/ms slew rate. Figure 1-2 shows the fault will have a glitch as V_IN ramp to about 1 V, which is far from the recommended operation range from 4.5 V to 5.5 V. Table 1-1 is the recommended operating condition of V_IN.

Figure 1-1 Bench Set-Up

Figure 1-2 Fault Glitch as Ramp V_IN at 6 V/ms

The following section discusses the root cause of this phenomenon and the solve method of this concern.

The following process occurs as V_IN ramps fast from 0 V to the recommended operation range:

• Before V_IN reach to UVLO threshold to start reset, the internal circuit status is unknown.
• If V_IN ramps pretty fast, the voltage on point B maybe coupled through C1.
• If the voltage on point B is larger than the threshold voltage V_th, T3 may pull down the FAULT pin.
• The whole circuit resumes to normal after the internal reset.

Figure 2-1 Simplified Internal Circuit Between IN Pin and Fault Pin

Due to the unknown status of the gate of T3, the Fault pin has the chance to be pulled down to 0 V.