Many battery-powered products such as wireless security cameras, video doorbells, and smart locks, are designed to have the option of running entirely off battery power, or with a battery and no other input power alternative. This allows users to install devices in any place of their choosing, regardless of the availability of a power socket nearby, and provide a more complete and discrete security coverage of their home.

Two challenges faced in the design of the system are reducing the amount of power lost in the power tree itself, and generating the power rails with minimal noise to meet peripheral input voltage noise requirements and improve performance. For example, a wireless security camera powered with two AA batteries requires less than 127 µA average system current (including both power-on and standby modes) to achieve two years of battery life. This can be calculated for any battery capacity and desired lifetime using Equation 1, which uses a 30% safety margin for the total battery capacity.

To achieve longer battery life, wireless or battery-powered cameras require a very low quiescent current (I_Q) and high efficiency at both full and light loads. These cameras typically employ motion detection, human interface, wireless communications monitoring, or any combination of the three to minimize time spent in power-hungry states. Because most of the device lifetime is spent in low-power states, quiescent currents, subsystem shutdown currents, and high efficiency are very important, as these standby currents can have significant impacts on overall battery life.

High voltage accuracy on the power rails is also a requirement, especially on rails that are powering core supply voltages, high speed I/O lines, and analog supplies. For HD video processing and streaming, the MPU is clocked at a very high speed, and employs a strict jitter budget. A noisy power supply to these high-speed lines induces jitter, thereby increasing bit error rate and degrading the quality of the high-speed signal. One example of this requirement is on the image sensor analog voltage, where it is necessary to ensure power supply noise is minimized to achieve a very high contrast ratio.

This document explores three different architectures for implementing high-efficiency, low-ripple buck converters for a battery-powered application, and the trade-offs for each. Possible solutions shown include: buck converter + LDO, forced pulse width modulation (FPWM) buck converter, and buck converter + PI filter. The performance of each is evaluated with respect to output voltage ripple, system efficiency at full and light loads, and I_Q.

Architecture A is implemented with the buck converter TLV62568 and the LDO TPS7A05.

TLV62568 is a high-efficiency, cost-effective buck converter utilizing an adaptive off-time with peak current control topology. The device operates at typically 1.5-MHz frequency PWM at moderate to heavy load currents. Based on the V_IN/V­_OUT ratio, a simple circuit sets the required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the variation of input voltage, output voltage, and load current. The current of the high-side switch is sensed for peak current control, and implements a switch current limit to prevent the device from drawing excessive current from a battery, or input voltage rail. Once the high-side switch current limit is reached, the high-side switch is turned off, and the low-side switch is turned on to ramp down the inductor current with an adaptive off-time.

TPS7A05 is an ultra-small, low quiescent current LDO that can source 200 mA with excellent transient performance. This device has an output range of 0.8 V to 3.3 V with a typical 1% accuracy. This LDO offers foldback current limit, shutdown, and thermal protection.

Architecture B is implemented with the FPWM version of the same buck converter from Architecture A, TLV62568A. As such, the control topology and functionality are essentially the same,but with the difference of TLV62568A staying in PWM mode at light loads while the TLV62568 goes into pulse frequency modulation (PFM) operation at light loads.

Architecture C is implemented with buck converter TPS62841, which has an ultra-low nominal I_Q of 60 nA, high light-load efficiency, and utilizes DCS-Control™. DCS–Control is a high-performance control scheme that combines the advantages of hysteretic and voltage mode controls. This combination allows for excellent AC load regulation and transient response, low output ripple voltage, and a seamless transition between PFM and PWM modes with minimum output voltage ripple. It includes an AC loop that senses the output voltage and directly feeds this information into a fast comparator stage. An additional voltage feedback loop is used to achieve accurate DC load regulation, and an internally compensated regulation network achieves fast and stable operation with small, external components and low ESR capacitors. In PFM, or Power-Save Mode, the switching frequency varies linearly with the load current.