SLVAEL7A December   2019  – August 2024 TPS7B7701-Q1 , TPS7B7702-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 Single-Channel FIT Rate
    2. 2.2 Dual-Channel Package FIT Rate
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 Single-Channel Package
    2. 4.2 Dual-Channel Package
  7. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the TPS7B770x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-6 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Figure 4-1 and Figure 4-2 show the TPS7B770x-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the TPS7B770x-Q1 data sheet.