The TPSM41625 is a fixed frequency buck power module that uses an internally compensated Advanced Current Mode (ACM) control scheme intended to simplify the design process. While the ACM scheme in TPSM41625 offers a ramp selection feature to tune the gain of the loop response, the fixed power stage inductor in the module and the finite internal compensation options result in minimum requirements on the output capacitor network for stable operation.

This application report will demonstrate how a combination of TPSM41625 ramp and reference settings, along with an external feedforward capacitor, can enhance the phase and gain margin of all ceramic, minimized output capacitor designs. While this report does not delve into the internal details of ACM control (1), measured loop response data is provided for an example design to illustrate the effect of output capacitance, ramp setting, and other design factors on TPSM41625 loop stability. Figure 1-1 shows the schematic of a 12-V input, 1.8-V output, 25-A, 500-kHz rail that is taken as the starting point for the design.

Figure 1-1 Original 12-V input, 1.8-V output, 25-A, 500-kHz design

Figure 2-1 shows the measured loop response of the TPSM41625 with different output capacitor configurations. The capacitor configurations span from the initial design shown in Figure 1-1, which is based on the TPSM41625EVM evaluation module and consists of a bulk 330-μF polymer (6TPE330MAA) and four 100-μF ceramic (GRM32EC70J107ME15L) capacitors, down to a design using only three of the same 100-μF ceramic capacitors.

Figure 2-1 Bode plot for different Cout (12-V input, 1.8-V output)

For the default evaluation module design, the bulk capacitor contributes an ESR zero which provides phase boost. The phase margin is almost 60° at the loop crossover frequency of 105 kHz where the gain curve crosses 0 dB. The phase curves are lower when the bulk capacitor (and the zero from the ESR) is removed. Decreasing the number of ceramic capacitors pushes the loop crossover frequency higher with decreasing phase margin.

With only 3 x 100 μF of nominal ceramic output capacitance, the loop crossover frequency is 148 kHz with a phase margin of 23° and gain margin of 8 dB. The typical recommendations are to have a minimum of 45° of phase margin and greater than 10 dB of gain margin. Furthermore, while crossover frequencies up to 1/5 of the switching frequency are acceptable for TPSM41625 designs, a crossover frequency of 148 kHz may be considered too high for a switching frequency (Fsw) of 500 kHz. The subsequent sections of this report show different adjustments that can be made to the design to stabilize the control loop for this 3 x 100 μF (300 μF) nominal ceramic output capacitor configuration.

The TPSM41625 provides RAMP and RAMP_SEL pins which can be used to program the internal ramp and tune the loop response. With the RAMP_SEL pin left open, an external resistor connected between RAMP and AGND sets the internal ramp. Connecting RAMP_SEL to AGND and leaving RAMP pin open will select the internal 78.7-kΩ resistor such that no external resistor is required. Figure 3-1 shows these connection options.

Figure 3-1 Ramp connection options

Figure 3-2 Bode plot for different ramp setting (12-V input, 1.8-V output)

The loop response for three different ramp settings is shown in Figure 3-2 for the 300-μF ceramic output capacitor configuration introduced in the previous section. As shown in the figure, decreasing the ramp resistor from 187 kΩ (the original value) to the lower options decreases the loop crossover frequency. A lower ramp resistor selects a lower internal ramp capacitor, which lowers the gain curve and thus the crossover frequency. With the internal 78.7-kΩ resistor selected, the crossover frequency has decreased from 148 kHz to 105 kHz and the gain margin has improved from 8 dB to 12.5 dB. However, in this case the phase curve has also shifted such that the phase margin is 24.5°, only a minor improvement compared to the 23° of phase margin with the 187-kΩ ramp setting. The following sections explore methods to increase the phase margin of this design with the internal 78.7-kΩ resistor selected.