D-CAP series control schemes are widely used in notebook, server, EP power and many other areas due to the advantages of good dynamic performance and less external components [1 and 2]. Different from the compensation with error amplifier in voltage mode and current mode, the zero formed by output capacitor ESR is used for loop compensation in the original D-CAP control [3 and 4]. With ESR zero after LC double poles, the slope of loop gain magnitude becomes -20dB/decade at crossover frequency, which ensures the system phase margin. For the application with MLCC or other small ESR capacitor, external or internal ripple injection circuit can be used to generate a zero instead of the ESR zero in D-CAP/D-CAP2/D-CAP3 control [5 and 6]. But if the inductor and output capacitor are not chosen properly and crossover frequency is lower than the frequency of ripple injection zero, a -40dB/decade slope at crossover frequency will happen and cause insufficient phase margin. An application design method is proposed for D-CAP2/D-CAP3 buck converter in this application report to ensure enough phase margin and system stability.

Figure 2-1 Control Diagram of D-CAP2 Converter

Diagram of buck converter with D-CAP2 control scheme is shown as Figure 2-1 . The open loop transfer function was derived in application report [2], as shown in Equation 1.

Equation 1.

where G_dv(s) is the transfer function from Duty to V_o, well known using state-space averaging model.

H_d(s) =e^-sTon/2: Delay factor of fixed on time

T_c: Time constant block of ripple injection circuit in D-CAP2

A_cp: Voltage compression block of ripple injection circuit in D-CAP2

H_FB(s): Transfer function of feedback divider network

The expression of G_dv(s) is shown as Equation 2.

Equation 2.

where

Equation 3.

R_L is the load resistance, r_L is DC resistance of the inductor, r_c is ESR of output capacitor.

A pair of double poles (conjugate poles) and a zero formed by ESR of output capacitor are included in the transfer function G_dv(s). The angular frequency of the double poles and the zero formed by ESR are shown as Equation 4 and Equation 5.

Equation 4.

Equation 5.

A zero is formed by the time constant block of ripple injection in D-CAP2 control mode, the angular frequency of the zero is:

Equation 6.

ω_esr is at high frequency range in most cases. ω₀ and ω_RI are the dominant poles and zero to determine bandwidth and phase margin. The bode plot of open loop transfer function for D-CAP2 converter is shown as Figure 2-2.

Figure 2-2 Bode plot of D-CAP2 Converter

To enhance DC accuracy of output voltage, D-CAP3 is proposed and widely used in TI’s current products. Compared with D-CAP2, the DC error correction performance is further improved in D-CAP3. By adding additional poles and zeros at low frequency range, the gain at low frequency range is increased to achieve better ability for DC error correction. But the characteristics of gain and phase at middle frequency and high frequency are almost same as D-CAP2 converter. The bode plot of open loop transfer function is shown as Figure 2-3.

Figure 2-3 Bode plot of D-CAP3 Converter

Phase margin is the phase at crossover frequency and it is one of the most important value for system stability evaluation. Since the crossover frequency is at middle frequency or high frequency, the impacts of additional zeros and poles at low frequency in D-CAP3 control mode on stability analysis can be ignored. Thus the application design method for D-CAP3 stability is same as that of D-CAP2. The analysis and design method in this application report can be applied on converters using either D-CAP2 or D-CAP3 control.

For system loop stability, a -20dB/decade slope near crossover frequency is ideal for loop gain, since that can bring sufficient phase margin [7].

In buck converters, the slope of open loop gain can be seen as -40dB/decade after double poles frequency ω₀. When the ripple injection zero frequency ω_RI is smaller than bandwidth, the loop gain will cross 0dB with -20dB/decade slope, as shown in Figure 3-1. Otherwise, it will cross 0dB with -40dB/decade slope, as shown in Figure 3-2.

Figure 3-1 Loop Gain of D-CAP2 Converter with -20dB/Decade at 0dB

Assuming the loop gain drops with -40dB/decade slope after ω₀, the cross frequency at 0dB is denoted as ω_c. From Figure 3-1 and Figure 3-2, it’s known that Equation 7 is needed for a -20dB/decade cross.

Equation 7.

To calculate the frequency ω_c, we can first get Equation 8 with ω_c

Equation 8.

Then ω_c can be derived as:

Equation 9.

Substituting Equation 4 and Equation 9 into Equation 7, Equation 10 can be derived to ensure -20dB/decade cross.

Equation 10.

If further considering the DCR of inductor r_L, Equation 10 will become:

Equation 11.

Since the inductance L is normally designed with the target to let inductor current ripple be about 20%-40% of max load current rating. With Equation 10 or Equation 11, the upper limit of capacitance value can be got for loop stability.

In D-CAP2/D-CAP3 control, A_cp and ω_RI are the parameters determined by the internal circuit inside converters. Table 3-1 shows the A_cp and ω_RI of some devices with D-CAP2 or D-CAP3 control.

Note: ω_RI is already given in some data sheets (sometimes named as time constant, it's the reciprocal of ω_RI). A_cp of a device can be estimated by checking the gain before double poles, which equals to 20lg(A_cp*V_ref/V_o)dB in bode plot.

From Equation 11, it can be found that smaller output capacitor tends to bring a -20dB/decade cross. But too small output capacitance will make the double poles frequency too high and increase the bandwidth a lot. That may also cause insufficient phase margin, since the phase will drop apparently at high frequency range due to the effects of delay factor. For D-CAP2/D-CAP3 mode converter, normally the bandwidth needs to be limited below 1/3*f_sw. That corresponds to a lower limit for output capacitance.

To get the limit, first we can get the loop gain at ripple injection zero in Figure 3-1 as:

Equation 12.

Loop gain will drop with -20dB/decade slope from A_RI and cross 0dB at ω_cross:

Equation 13.

Limit the crossover frequency below 1/3*f_sw and the lower limit of output capacitance can be derived as Equation 15.

Equation 14.

Equation 15.

Above all, the Equation 11 and Equation 15 are the upper limit and lower limit of output capacitance for loop stability.