SLVAF11 June   2021 TPS51397A , TPS566231 , TPS566235 , TPS566238 , TPS568230

 

  1.   Trademarks
  2. 1Introduction
  3. 2Open Loop Frequency Response of D-CAP2 and D-CAP3 Converter
  4. 3Method to Choose LC Value for Loop Stability
    1. 3.1 Limits of Output Capacitance
    2. 3.2 Phase Margin Estimation Method
  5. 4Example of LC Design Method for D-CAP3 Converter
  6. 5Simulation and Experimental Verification
  7. 6Summary
  8. 7References
  9. 8Appendix A

8 Appendix A

For TPS568230 Ioutmax=8A, Vref=0.6V. PM is the phase margin of converter. All the capacitors used in the validation are MLCC. With POSCAP or electrolytic capacitors, the phase margin can be boosted with ESR zero and that could bring larger range of output capacitance values.

Table 8-1 Validation Results for the Proposed Methods
Vin (V) Vo (V) fsw (kHz) Llimits (uH) Lchoose(uH) Climits (uF) Cchoose(uF) PMestimated PMexperiment
60.96000.4-0.80.6885-39337647.1°52.9°
61.26000.5-10.6864-29728245.8°51.9°
61.56000.59-1.17134-15813248.5°46.9°
61.86000.66-1.31128-12911046.7°47.1°
180.96000.45-0.890.6885-39337649.3°53.9°
181.26000.58-1.17143-20018852.6°54.4°
181.86000.84-1.691.519-898854.2°48.1°