SLVAF11 June   2021 TPS51397A , TPS566231 , TPS566235 , TPS566238 , TPS568230

 

  1.   Trademarks
  2. 1Introduction
  3. 2Open Loop Frequency Response of D-CAP2 and D-CAP3 Converter
  4. 3Method to Choose LC Value for Loop Stability
    1. 3.1 Limits of Output Capacitance
    2. 3.2 Phase Margin Estimation Method
  5. 4Example of LC Design Method for D-CAP3 Converter
  6. 5Simulation and Experimental Verification
  7. 6Summary
  8. 7References
  9. 8Appendix A

1 Introduction

D-CAP series control schemes are widely used in notebook, server, EP power and many other areas due to the advantages of good dynamic performance and less external components [1 and 2]. Different from the compensation with error amplifier in voltage mode and current mode, the zero formed by output capacitor ESR is used for loop compensation in the original D-CAP control [3 and 4]. With ESR zero after LC double poles, the slope of loop gain magnitude becomes -20dB/decade at crossover frequency, which ensures the system phase margin. For the application with MLCC or other small ESR capacitor, external or internal ripple injection circuit can be used to generate a zero instead of the ESR zero in D-CAP/D-CAP2/D-CAP3 control [5 and 6]. But if the inductor and output capacitor are not chosen properly and crossover frequency is lower than the frequency of ripple injection zero, a -40dB/decade slope at crossover frequency will happen and cause insufficient phase margin. An application design method is proposed for D-CAP2/D-CAP3 buck converter in this application report to ensure enough phase margin and system stability.