5 Design Approaches to Improve the Load Release Characteristics of SoC Chipset

General approaches to improve the load release are to move the input capacitor to device input pin or adding more input capacitors or adding Rboot in series with Cboot or add more output capacitors to achieve fast load transient. However, it doesn’t work to reduce the overshoot voltage in the application. Instead when adding schottky diode (SX34) on HSFET for current bypass, it can reduce the positive overshoot voltage but it makes a negative ringing voltage higher as shown in Figure 5-1.

When adding RC snubber (3.3 ohm + 470pF) on PH node to damp the parasitic inductances and capacitances during the switching transitions, the overshoot voltage is reduced down to 7.7 V peak as shown in Figure 5-2.

Another approach is to extend TPS5432 loop bandwidth with optimizing compensation RC values in the application without adding external circuits such as schottky diode and RC snubber. Extending the loop bandwidth can achieve a fast load transient response as shown in Figure 5-3. OVT (pulse skip) and RCP is still observed when the loop bandwidth is 12kHz as shown in Figure 5-3 (left). There is still OVT (Shorter pulse skip time) when the loop bandwidth is 25kHz as shown in Figure 5-3 (middle). However, when the loop bandwidth is 37.57kHz, OVT and RCP is not observed in Figure 5-3 (right). In addition, there is no overshoot voltage on PH node any more.