The analog and clock inputs of converter often get most of the scrutiny when it comes to addressing low noise on their inputs. Keep in mind that power supplies are inputs too. Because we think of them as DC biasing circuits we often do not think of them as affecting RF performance. However, this is not true. Spurious performance is dependent on the layout structure. The DC-DC converters are generating switching spurious which can be large.

Switching spurious infiltrate unwanted circuits via conducted paths or radiated paths. Conducted spurious are mitigated with the ferrite bead isolation, supply filtering, and adequate low frequency bypass capacitors. Radiated emissions are more difficult to control.

The primary location for radiated emissions is right at the DC-DC converter itself and the switching inductor. Since the switching spurious are large in amplitude and at low frequency, localized shielding or PCB ground planes do little to attenuate the spurious. Switching spurious penetrate ground planes easily and infect internal, sensitive power traces. As such, keep sensitive routing from running on an internal layer directly underneath the DC-DC converter. Further, no other board with sensitive internal nets should be placed directly above or below. Even physical spacing as much as one inch is not sufficient to reduce the spurious coupling. Instead, the DC-DC switchers should be offset from any sensitive area or other boards so that there is nothing directly above or below the converters that will be contaminated by switching spurious. When designing power supply domains for any high-speed converter, here are some useful tips in maximizing power supply noise immunity:

• Decouple all power supply rails and bus voltages as they come onto the system board near the AFE itself.
• Remember that approximately 20-dB/decade noise suppression is gained for each additional filtering stage.
• Decouple both high and low frequencies, which might require multiple capacitor values.
• Series ferrite beads are commonly used at the power entry point just before the decoupling capacitor to ground. This should be done for each individual supply voltage coming into the system board regardless of whether it comes from an LDO or switching regulator.
• For added capacitance, use tightly stacked power and ground plane pairs (≤ 4-mil spacing). This adds inherent high-frequency (> 500 MHz) decoupling to the PCB design.
• Keep supplies away from sensitive analog circuitry such as the front-end stage of the AFE and clocking circuits if possible.
• Follow the IC manufacture recommendations; if they are not directly stated in the application note or data sheet, then study the evaluation board. These are great vehicles to learn from.

Applying the above points help provide a solid power supply design yielding data sheet performance in many applications.