SLVAFA2 February 2022 TPS1HC100-Q1
Table 3-1 describes the integrated circuits used to construct the TPS1HC100 Power Distribution Board and provides a quick summary of their purpose.
| Part Number | Qty | Purpose |
|---|---|---|
| TPS1HC100-Q1 | 8 | High side switch for 2-A max load, each |
| TPL0102 | 8 | Set unique RSNS, RILIM for each TPS1HC100-Q1 |
| TCA9539-Q1 | 1 | IO expansion, controls DIA_EN, LATCH for each TPS1HC100-Q1 |
| TPS629210-Q1 | 1 | Convert battery voltage to 3.3-V system VDD |
The TP1HC100 power distribution module is constructed of 4-2-oz copper layers with an FR4 core and PP-006 prepreg. 2-oz copper was chosen to reduce current crowding in the power path (VBB and GND). GND is constructed as an inner plane layer both for ease of routing and current distribution, while VBB is routed as polygons on the top and bottom layer to minimize path impedance. Both GND and VBB signals utilize via stitching to mitigate bottlenecks during layer changes. The other inner layer serves as a plane for VDD exclusively to alleviate routing constraints. Finally, the top layer is primarily a low current signal layer for fanning out IO signals from the CC2652R7 LaunchPad to the peripheral ICs. Additional low-power signal routing was moved to the VDD plane and bottom layers as top-layer space grew limited. IC_GND is routed on the top layer as a polygon pour to provide thermal mass to dissipate heat from each of the TPS1HC100 devices.
There are a total of 18 integrated circuits on the distribution module. 8-TPS1HC100-Q1 are used to drive 8 loads, up to 2-A DC each. Each TPS1HC100-Q1 is paired with a TPL0102 2CH I2C-enabled digital potentiometer. Each of the 8 TPL0102 are used to set RSNS and RILIM in lieu of discrete resistors. This allows for software controllable resistances in the event a new load is desired for a given channel. RSNS and RILIM can be resized in software to best suit whichever load is applied. TPL0102 has 3 address pins to avoid address conflicts on the I2C bus. A single TCA9539-Q1 I2C-GPIO expander is placed to provide additional digital IO between the CC2652R7Launchpad and each TPS1HC100-Q1. TCA9539-Q1 communicates over the I2C bus to set or read any of it’s 16 IO pins. In this instance all IO pins are set as output to control the DIAG_EN and LATCH pins of each channel. These pins typically do not have strict timing requirements, so the time to send an I2C transaction does not drastically impact the performance of the system. In contrast, EN pins are connected directly to the LaunchPad for more precise timing/PWM control.
Finally, a TPS629210-Q1 1A adjustable VOUT buck-converter is used to provide 3.3 V to the TCA9539-Q1, 8-TPL0102, and CC2652R7 LaunchPad. A buck-converter was selected over linear regulator to reduce losses in the voltage conversion. For example, the system has an idle current draw of 30 mA. Assuming 90% efficiency with TPS629210-Q1, PLOSS = PIN-POUT = PIN-0.9*PIN … PLOSS = 0.1*PIN = 0.1*(12 V*0.03 A) = 36 mW. Contrast this with an LDO, where power can be approximated as PLOSS = (VIN-VOUT)*IIN = (12 V-3.3 V)*.03 A = 261 mW.
TPS1HC100-Q1 is powered directly from the automotive battery/DC supply. All other ICs and the launchpad receive power via the TPS269210-Q1 3.3 V output. This output level also dictates the logic level and FLT voltage level in the system. TI LaunchPads come populated with 2 sets of 100mil headers. A matching set of headers was placed on the TPS1HC100 Power Distribution Module to create a clean interface for all signals to/from each board. There are five signals that must be communicated between each TPS1HC100-Q1 and the CC2652R7 LaunchPad – EN, DIAG_EN, LATCH, FLT, and SNS. The interface between each signal is as follows:
EN and FLT are directly connected to the LaunchPad since these signals are most time critical. For example, the user may want to control their load with a pulse width modulated EN signal, which would not be feasible over the I2C bus. Additionally, FLT might be used to trigger an interrupt. Detection is quicker with a digital edge at the uC rather than an I2C transaction. Finally, SNS is connected to an ADC input since it is an analog signal