SLVAFE9 September 2022 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , TPS65219 , TPS65220
There are five different orderable part number (OPN) variants of the TPS65220 and TPS65219 PMIC that come factory programmed to power the AM64x processor. Selecting the right OPN will be based on the application use case and design requirements. Table 3-1 compares the NVM configurations from the output voltages on each rail to the configuration of the digital pins as well as the package options. This table also includes the reference hardware that is available to support new designs. For additional detailed information, please refer to the device data sheet and technical reference manual (TRM) available at TI.com.
| TPS6522053 Section 4 | TPS6521901 Section 4.1 | TPS6521902 Section 4.2 | TPS6521903 Section 4.3 | TPS6521904 Section 4.4 | ||
|---|---|---|---|---|---|---|
| Use Case | Vsys | 3.3V | 5 V | 3.3 V | 3.3 V | 3.3 V |
| External Memory Support | LPDDR4 | DDR4 | LPDDR4 | DDR4 | DDR4 | |
| BUCK1 | Vout | 0.75V | 0.75 V | 0.75 V | 0.75 V | 0.85 V |
| Bandwidth | High Bandwidth | High bandwidth | High bandwidth | High bandwidth | High bandwidth | |
| BUCK2 | Vout | 1.8 V | 3.3 V | 1.8 V | 1.8 V | 1.8 V |
| Bandwidth | High Bandwidth | High bandwidth | High bandwidth | High bandwidth | High bandwidth | |
| BUCK3 | Vout | 1.1 V | 1.2 V | 1.1 V | 1.2 V | 1.2 V |
| Bandwidth | High Bandwidth | High bandwidth | High bandwidth | High bandwidth | High bandwidth | |
| LDO1 | Vout | 3.3 V (Bypass) | 3.3 V (Bypass) | 3.3 V (Bypass) | 3.3 V (Bypass) | 3.3 V (Bypass) |
| LDO2 | Vout | 0.85 V | 0.85 V | 0.85 V | 0.85 V | 1.8 V (Bypass) |
| LDO3 | Vout | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| LDO4 | Vout | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 2.5 V |
| GPIO | GPO1 | Disabled | Enabled | Disabled | Disabled | Disabled |
| GPO2 | Enabled | Disabled | Enabled | Enabled | Enabled | |
| GPIO | Disabled | Disabled | Disabled | Disabled | Disabled | |
| Multi-Device | Disabled | Disabled | Disabled | Disabled | Disabled | |
| MODE_RESET | Config | Warm reset | Warm reset | Warm reset | Warm reset | Warm reset |
| MODE_STANDBY | Config | Mode and Standby | Mode and Standby | Mode and Standby | Mode and Standby | Mode and Standby |
| VSEL_SD_DDR | Config | SD | SD | SD | SD | SD |
| Polarity | High = VOUT Low = 1.8 V | High = VOUT Low = 1.8 V | High = VOUT Low = 1.8 V | High = VOUT Low = 1.8 V | High = VOUT Low = 1.8 V | |
| Rail | LDO1 | LDO1 | LDO1 | LDO1 | LDO1 | |
| EN_PB_VSENSE | Config | Enable | Enable | Push-button | Push-button | Push-button |
| First Supply detection [1] | FSD config | Enabled | Enabled | Enabled | Enabled | Enabled |
| Additional Features | Temperature Range | TA : -40˚C to 125˚C TJ : -40˚C to 150˚C | TA : -40˚C to 105˚C TJ : -40˚C to 125˚C | TA : -40˚C to 105˚C TJ : -40˚C to 125˚C | TA : -40˚C to 105˚C TJ : -40˚C to 125˚C | TA : -40˚C to 105˚C TJ : -40˚C to 125˚C |
| Functional Safety Capable | Yes | No | No | No | No | |
| Orderable Part Number | Package size 5 x 5 mm | TPS6522053RHBR | TPS6521901RHBR | TPS6521902RHBR | TPS6521903RHBR | TPS6521904RHBR |
| Package size 4 x 4 mm | N/A | TPS6521901RSMR | TPS6521902RSMR | TPS6521903RSMR | TPS6521904RSMR | |
| Design Resources | Reference Hardware | SK-AM64B EVM | TPS65219EVM (PMIC only. Does not include processor) | N/A | N/A | N/A |
| Reference Hardware Availability | Boards available on Ti.com starting September 2022. | Boards and design files available now on Ti.com. | N/A | N/A | N/A |
[1] First Supply detection allows power-up as soon as supply voltage is applied, even if EN/PB/VSENSE pin is at OFF_REQ status. FSD can be used in combination with any ON-request configuration, EN, PB or VSENSE. At first power-up the EN/PB/VSENSE pin is treated as if it had a valid ON request.