4 TPS6522053 Powering AM64x

Use case: VSYS=3.3V, LPDDR4 Memory, Extended Temperature Range, Functional Safety Capable

Figure 4-1 shows the TPS6522053 variant powering the AM64x processor on a system with 3.3 V input supply and LPDDR4 memory. The 3.3 V coming from the pre-regulator is connected to the main input supply for reference system (VSYS) and to the power input of the buck converters (PVIN_Bx) and LDO1, LDO3, and LDO4 (PVIN_LDO1, PVIN_LDO34). The 3.3 V coming from the pre-regulator can be combined with a power switch to supply the 3.3 V VDDSHVx IO domain. Buck1 is used to supply VDD_CORE at 0.75 V. Buck3 and Buck2 supports the 1.1 V and 1.8 V required by VDDS_DDR and the DVDD1V8 domain. They are also used to support the required voltages on the LPDDR4 memory. The GPO2 is pre-programmed to be enabled in the second slot of the power-up sequence with a duration of 6ms. It can be used to enable the external power switch and meet the processor sequence requirements. The switch must be selected with the right electrical spec to ramp and provide a stable output voltage within the 6ms duration of the second slot (before the PMIC starts the next slot in the power-up sequence). LDO1, configured as bypass, allows dynamic SD card voltage changes between 3.3 V and 1.8 V. This voltage change on LDO1 can be triggered by I2C or by setting the VSEL_SD pin high (LDO1=3.3 V) or low (LDO1=1.8 V). LDO2, is used to supply the VDDR_CORE. LDO3 supports the 1.8 V analog domain. LDO4 is a free 2.5 V power resource that can be used for external peripherals like the Ethernet PHY. GPIO and GPO1 are free digital resources that are disabled by default but could be enabled through I2C if needed. Figure 4-2 and Figure 4-3 shows the power-up and power-down sequence programmed on TPS6522053.