Figure 4-10 shows the TPS6521903 variant powering the AM64x processor on a system with 3.3 V input supply and DDR4 memory. Buck1, Buck2, LDO3, LDO2, LDO1, and GPO2 are used to power/enable the same domains that were described in the previous power block diagrams. The 3.3 V, coming from the pre-regulator, can be combined with a power switch to supply the 3.3 V VDDSHVx IO domain. The GPO2 is pre-programmed to be enabled in the second slot of the power-up sequence with a duration of 10 ms. It can be used to enable the external power switch and meet the processor sequence requirements. The switch must be selected with the right electrical spec to ramp and provide a stable output voltage within the 10 ms duration of the second slot (before the PMIC start the next slot in the power-up sequence. Buck3 is used to supply the VDDS_DDR and together with the 1.8 V on Buck2 they support the voltages needed for the DDR4 memory. GPIO and GPO1 are free digital resources that are disable by default but could be enabled through I2C if needed. Figure 4-11 and Figure 4-12 shows the power-up and power-down sequence programmed on TPS6521903.