SLVAFF7B December   2022  – November 2024 TPS25762-Q1 , TPS25763-Q1 , TPS25772-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Purpose and Scope
  5. 2Firmware Boot Code Brief
  6. 3Patch Bundle Brief
  7. 4Firmware Update
    1. 4.1 Overview
    2. 4.2 EEPROM Firmware Update
      1. 4.2.1 EEPROM Memory Organization
      2. 4.2.2 EEPROM Update - 4CC Task Command Set
      3. 4.2.3 EEPROM Patch Bundle Update Process
    3. 4.3 PD Controller Patch Bundle Download
      1. 4.3.1 Patch Bundle Download - 4CC Task Command Set
      2. 4.3.2 Burst Mode Patch Download Process
  8.   Appendix A: TVSP Boot Configuration Settings
  9.   Appendix B: Using 4CC Commands
  10.   Revision History

Appendix B: Using 4CC Commands

4CC (4-byte character code) commands are a set of commands that simplify the use of the PD controller's commonly used functions. It allows the user to send a single task that manages more complex subroutines and function specific register writes for them.

The 4CC command structure is similar to a software function, where you have input arguments (Input DATAx), a function call (writing the 4CC command to the CMDx register), and a returned output (Output DATAx).

The 4CC commands that are written to the CMDx register are obtained by converting the 4-character commands to ASCII. You can use an ASCII converter to help you translate the codes (for example, the 4CC command PBMs is converted to 50 42 4D 73). Please keep in mind that the commands are case-sensitive.

The CMD1 (0x08) register will have the 4CC commands written to it over the I2C1 bus. Any Data (Input DATAx, Output DATAx) is written to or read from the DATA1 (0x09) register. There is a second set of registers for the I2C2 bus at 0x10, for CMD2, and 0x11, for DATA2. Table 5-1 provides detailed Unique Address Interface descriptions.

Table B-1 Unique Address Interface Registers
Register Address Register Name Access Description
0x03 MODE RO Indicates the operational state of the port.
0x08 CMD1 RW Command register for the primary command interface. If an unrecognized command is written to this register, it is replaced by a 4CC value of "!CMD".
0x09 DATA1 RW Data register for the primary command interface (CMD1).
0x10 CMD2 RW Command register for the secondary command interface. If an unrecognized command is written to this register, it is replaced by a 4CC value of "!CMD".
0x11 DATA2 RW Data register for the secondary command interface (CMD2).
0x14 INT_EVENT1 RO Interrupt event bit field for I2C_EC_IRQ. If any bit in this register is 1, then the I2C_EC_IRQ pin is pulled low.
0x15 INT_EVENT2 RO Interrupt event bit field for I2C2s_IRQ. If any bit in this register is 1, then the I2C2s_IRQ pin is pulled low.