SLVAFF7B December   2022  – November 2024 TPS25762-Q1 , TPS25763-Q1 , TPS25772-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Purpose and Scope
  5. 2Firmware Boot Code Brief
  6. 3Patch Bundle Brief
  7. 4Firmware Update
    1. 4.1 Overview
    2. 4.2 EEPROM Firmware Update
      1. 4.2.1 EEPROM Memory Organization
      2. 4.2.2 EEPROM Update - 4CC Task Command Set
      3. 4.2.3 EEPROM Patch Bundle Update Process
    3. 4.3 PD Controller Patch Bundle Download
      1. 4.3.1 Patch Bundle Download - 4CC Task Command Set
      2. 4.3.2 Burst Mode Patch Download Process
  8.   Appendix A: TVSP Boot Configuration Settings
  9.   Appendix B: Using 4CC Commands
  10.   Revision History

4.2.1 EEPROM Memory Organization

The patch bundle of the device can be contained in the memory of the EEPROM NVM IC. The organization of this data in EEPROM is explained in this section using variables and relative locations. Memory organization might differ between the variants of device, and the application developers shall account for these differences when developing the EEPROM-update applications for the device.

In this application note, the memory organization of an EEPROM is explained based on the assumption that the EEPROM is dedicated to the device and not shared with other ICs of the system. For redundancy, the patch bundle is copied into two regions; Region-0 (low region) and Region-1 (high region). If the full memory of the EEPROM is read directly, it will contain region-headers and regions, which will simply be referred to as an eeprom.bin file. A depiction of the full eeprom.bin EEPROM memory organization for the device is shown in Figure 4-3.

EEPROM Memory Organization of Region-0 (Low Region) and Region-1 (High Region)Figure 4-3 EEPROM Memory Organization of Region-0 (Low Region) and Region-1 (High Region)

The external EEPROM shall be programmed with a full eeprom.bin the first time the platform is powered up so that the region headers are set up correctly. The subsequent EEPROM-update can be executed by the external hosts by following the sequence detailed in subsequent sections. A full eeprom.bin can be generated using the device’s application customization tool, TPS257XX-Q1-GUI. When you generate a full eeprom.bin by using the GUI, the region offsets for Region-0 and Region-1 will be set automatically.

By using 4CC commands, we can update the EEPROM from a host controller such as an MCU. In Figure 4-3, the first two blocks are headers for Region-0 and Region-1. Each header needs 128B of space. A header is used to indicate the start address of the patch bundle, and it consists of an address base and an address offset. The first four bytes of the header is the address base, and the last four bytes of the header is the address offset. Thus, the actual start address of the patch bundle is the address base plus address offset.

A patch bundle consists of patch bundle header, customized configuration data, and patch codes. The patch bundle for Region-0 and Region-1 are completely the same as previously mentioned.