SLVAFJ9 March 2023 TPSF12C1 , TPSF12C1-Q1 , TPSF12C3 , TPSF12C3-Q1
Figure 9-1 shows practical AEF implementations for CM attenuation with a FB-VSCI configuration using the TPSF12C1, TPSF12C1-Q1, TPSF12C3 and TPSF12C3-Q1 stand-alone AEF IC family in single- and three-phase power systems [8-11]. The setups are similar to the two-stage passive filters in Figure 4-1, except that the AEF IC is now positioned between the CM chokes to provide a lower-impedance shunt path for CM currents.
The sense pins of this device family interface with the power lines using a set of Y-rated sense capacitors, typically 680 pF, and feed into a high-pass filter and signal combiner, as shown in the IC block diagram of Figure 9-2. The IC rejects both the line-frequency (50- or 60-Hz) AC voltage as well as DM disturbances, while amplifying high-frequency CM disturbances and maintaining closed-loop stability using an external tunable damping circuit.
The components between the COMP1 and COMP2 pins form a lead-lag network that sets the amplification gain characteristic. The output of the power amplifier at INJ injects the required noise-canceling signal back into the power lines through a damping and stability network (see components with subscript āDā reference designators in Figure 9-1), and a Y-rated injection capacitor CINJ, typically 4.7 nF. The IC includes integrated filtering, compensation and protection circuitry. The VDD bias supply ranges from 8 V to 16 V, nominally 12 V, and references to system chassis ground.
The X-capacitor(s) placed between the two CM chokes effectively provide a low-impedance path between the power lines from a CM standpoint, typically up to low-megahertz frequencies. This path allows current injection onto one power line, typically neutral, using only one injection capacitor. If the three-phase filter is a three-wire system without a neutral wire, the SENSE4 pin of the TPSF12C3-Q1 ties to ground and the injection capacitor couples through an artificial star-point connection of the X-capacitors.